Hideo Hara
Hitachi
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Publication
Featured researches published by Hideo Hara.
Microelectronics Journal | 1984
Hideo Hara; Takashi Akazawa; Yoshimune Hagiwara
The HSP (HD61810) is a single-chip digital signal processor which includes a high speed arithmetic logic unit, a high speed multiplier, and a large memory on a single silicon chip. Its architecture features floating point arithmetic and a pipeline structure. With the floating point arithmetic operation, the HSP can manipulate a wide dynamic range of data. The instruction cycle of the HSP is 250 ns. One multiply/add operation can be executed per cycle. The HSP uses 3 μm CMOS technology and so achieves low power consumption. It is programmed by an internal instruction ROM.
Archive | 2002
Yoji Nishio; Kosaku Hirose; Hideo Hara; Katsunori Koike; Kayoko Nemoto; Tatsumi Yamauchi; Fumio Murabayashi; Hiromichi Yamada
Archive | 1983
Katsuaki Takagi; Yuzo Kita; Yoshimune Hagiwara; Kazuyoshi Ogawa; Hideo Hara
Archive | 1975
Hiroshi Goto; Toshiharu Arai; Tadao Sekiguchi; Hideo Hara
Archive | 1983
Katsuaki Takagi; Yuzo Kita; Yoshimune Hagiwara; Kazuyoshi Ogawa; Hideo Hara
Archive | 1995
Hideo Hara; Tatsuya Houmoto; Kunihiko Karasawa; Hiroshi Murakami; 英夫 原; 国彦 唐沢; 博志 村上; 竜也 法本
Archive | 1995
Hideo Hara; Kosaku Hirose; Katsunori Koike; Fumio Murabayashi; Kayoko Nemoto; Yoji Nishio; Hiromichi Yamada; Tatsumi Yamauchi; 英夫 原; 勝則 小池; 辰美 山内; 弘道 山田; 晃作 廣瀬; 文夫 村林; 佳代子 根本; 洋二 西尾
Archive | 2012
Hideo Hara; 英夫 原
Archive | 2011
Haruo Yamakoshi; 陽夫 山越; Hideo Hara; 英夫 原
Archive | 2006
Hideo Hara; Keiji Hayashi; Toru Inamasu; Kazuto Okumura; Yoshikazu Tanaka; 英夫 原; 和人 奥村; 圭治 林; 良和 田中; 亨 稲益
