Hiep V. Tran

A 1 V DSP for wireless communications

Modern cellular phones are placing increasingly stringent demands on battery life and, therefore, on the power dissipation of the embedded DSP circuitry. At the same time, greater computational throughput is being required of the DSP, for example to implement more sophisticated speech and channel coding algorithms. Earlier low-power DSPs were reported. However, further improvements in power and performance are required. This paper describes a full-function, 1.6M-transistor, fixed-point programmable DSP designed for wireless communication applications to address these dual constraints of lower power and higher throughput. This is achieved by operating at 1V and using a dual-V process to maintain high performance.

Demonstration of 5T SRAM and 6T dual-port RAM cell arrays

This paper describes new circuit techniques that provide robust operations for a five transistor, single bitline SRAM cell design. The techniques have been implemented in an array of six transistor memory cells and operated as a dual-port RAM. The array has been fabricated using 0.6 /spl mu/m CMOS technology, and the test results show the array is capable of operating as a dual-port memory over a wide voltage supply range.

An 8 ns BiCMOS 1 Mb ECL SRAM with a configurable memory array size

A 1-Mb*1 BiCMOS ECL (emitter-coupled-logic) I/O SRAM (static random access memory) is fabricated using a 0.8- mu m BiCMOS process. This memory device utilizes a 76- mu m/sup 2/ full-CMOS six-transistor memory cell, a dual-MOS current-source BiCMOS bit line sensing scheme, a BiCMOS current-source voltage reference network, and a low-capacitance load block line decoding circuit to achieve 8-ns access time. The configurable memory array size architecture allows for memory sizes from 64 kb up to 1 Mb in 64 kb increments with no change in the peripheral circuits. The six-transistor cell layout is shown, and the memory block architecture is illustrated. The low dependence of power supply current on the operating frequency shows the impact of ECL circuits in the design. Characteristics of the SRAM are summarized.<<ETX>>

Circuit techniques for a wide world I/O path 64 Meg DRAM

The high rate data transfer between CPU and memory in future high performance systems requires the 64 Meg DRAM and generations beyond to take a new design approach. Fast RAS access time together with a wider I/O path are key DRAM performances indices for achieving high bandwidth CPU-MEMORY data operations. A novel Hierarchical Multi-Datalines (HMD) Architecture with a wide I/O path and high speed circuit design techniques used to implement this architecture in a 64 Meg DRAM are described.<<ETX>>

BiCMOS current source reference network for ULSI BiCMOS with ECL circuitry

A BiCMOS current source reference network which eliminates the impact of DC power supply voltage drops on the operation of ECL (emitter coupled logic) circuits is described. This is essential for implementing ECL design techniques in ULSI BiCMOS circuits. Using the current source network, reference voltages are generated locally, so that the ECL voltage references are correctly referenced to the local power supply potentials. A power-supply-insensitive bandgap reference generator is used to generate precision on-chip voltage references and current sources. The bandgap reference circuit uses both MOS and bipolar transistors and is much simpler than a similar design using bipolar-only circuitry. The micrograph of the test chip containing the bandgap circuit nd BiCMOS op amp analog drivers is shown. The drivers are designed for multiple-reference-level regeneration. The test chip has been fabricated using a 0.8- mu m BiCMOS process. The typical characteristics of the bandgap circuit and the analog driver are shown.<<ETX>>

An experimental 5 ns BiCMOS SRAM with a high-speed architecture

A RAM which uses circuit techniques and architectural innovation to achieve the performance demanded by todays systems is described. An input buffer/level translator, a current sense amplifier, and a high-speed architecture are used in this RAM to achieve the 5-ns access time along with the 0.6-&mu;m BiCMOS technology. The chip is organized as 128 K-words&times;8-b wide using a 4T2R memory cell of 28 &mu;m2

Impact of BiCMOS technology on SRAM circuit design

The BiCMOS design techniques used in the design of ECL (emitter-coupled logic) megabit and 256 K BiCMOS SRAMs are discussed. The topics covered include design issues with respect to ECL-to-CMOS-level translation, sense amplifier design, I/O interface issues, and the integration of bipolar devices into high-density, but traditionally CMOS-only circuits. The superior performance that BiCMOS has over CMOS with respect to temperature insensitivity is discussed.<<ETX>>

Charge-delay (Qt) as a performance metric for low-power CMOS circuit design

The advent of low-power design has created a need for a metric (Figure of Merit) that is convenient to use in technical communications as well as a design guide. This paper examines a few common metrics for evaluating low-power CMOS circuit design effectiveness. It identifies charge-delay product (Qt) as a convenient and balanced metric. This function has an optimum point offering a better criterion than other common metrics for circuits that have operating margins that depend on the circuit delays.

BiCMOS Standard Memories

Over the past few years, memory performance has been the primary demonstration vehicle for BiCMOS technologies. Intrinsic gate delay, power dissipation and area have been regarded as the theoretical indications for technology performance and density. In a similar manner memory access time, memory power dissipation and memory size have been regarded as the practical indications of technology performance and density. Against this empirical yard stick BiCMOS technology has been found to produce memories with MOS-like power and density but with speeds and I/O interfaces which one normally attributes to bipolar memories.

A 0.5- mu m BiCMOS technology for logic and 4 Mbit-class SRAMs

The authors describe a 0.5- mu m BiCMOS technology for high-performance logic and SRAMs (static RAMs) which is capable of supporting 5-V hot-carrier-hard circuit designs. In these designs the maximum drain-to-source voltage across a 0.5- mu m NMOS device is restricted to 4 V to ensure hot carrier reliability using 12-nm gate oxide. However, for the bipolar device, isolation and longer channel MOS devices, the process is required to support 5 V. For a 5-V supply voltage, the capacitive load drive factor for a BiCMOS NAND gate is 160 ps/pF, which is 30% smaller than the load drive factor for the same basic design gate built using an 0.8- mu m process with 20-nm gate oxide. The authors also discuss how a vertical NMOS driver transistor and a polysilicon PMOS load device are integrated into the 0.5- mu m BiCMOS process. The addition of these components permits a 23- mu m/sup 2/ stacked 6-T CMOS SRAM cell to be realized, suitable for 4-Mb-class BiCMOS SRAMs.<<ETX>>