Roger A. Haken

0.5 micron CMOS for high performance at 3.3 V

In addition to higher packing density, the scaling of CMOS technology to the half-micron regime must provide improved circuit performance at a reduced supply voltage without increased process complexity. These goals have been met with a 0.5- mu m CMOS technology with 12-nm gate oxide thickness that gives at least a 20% speed improvement at a 3.3-V supply voltage compared to an 0.8- mu m technology at 5.0 V with 20-nm gate oxide. Adequate process margin is obtained by requiring that transistors patterned 0.1 mu m shorter than design length fully meet the requirements for minimum short-channel leakage and sensitivity to hot-carrier stress.<<ETX>>

An 0.8&#181;m CMOS technology for high performance logic applications

This paper reports on the process architecture and results of an 0.8µm 5V CMOS logic technology. The process, which is a factor of two faster than current 1.2µm CMOS technology, features seven optically patterned levels with 0.8µm geometries: isolation, gates, contacts, vias, TiN local interconnect (LI), and two metal levels.

An 8 ns BiCMOS 1 Mb ECL SRAM with a configurable memory array size

A 1-Mb*1 BiCMOS ECL (emitter-coupled-logic) I/O SRAM (static random access memory) is fabricated using a 0.8- mu m BiCMOS process. This memory device utilizes a 76- mu m/sup 2/ full-CMOS six-transistor memory cell, a dual-MOS current-source BiCMOS bit line sensing scheme, a BiCMOS current-source voltage reference network, and a low-capacitance load block line decoding circuit to achieve 8-ns access time. The configurable memory array size architecture allows for memory sizes from 64 kb up to 1 Mb in 64 kb increments with no change in the peripheral circuits. The six-transistor cell layout is shown, and the memory block architecture is illustrated. The low dependence of power supply current on the operating frequency shows the impact of ECL circuits in the design. Characteristics of the SRAM are summarized.<<ETX>>

VLSI Local interconnect level using titanium nitride

A local interconnect technology has been developed for VLSI CMOS applications using a titanium nitride layer. The technology has been realized by utilizing the titanium nitride layer that forms during the self-aligned titanium silicide process: which is used to simultanously reduce gate and junction sheet resistances to < 1 ohm/sq. Normally the TiN layer is discarded, but in this process the 0.1µm thick TiN layer is patterned and etched to provide local connections between gates and N+ and P+ junctions, with a sheet resistance of < 10 ohm/sq. This is accomplished without area consuming contacts or metal straps, and without any additional deposition steps, in addition to providing a VLSI version of the buried contact process, the technology results in self-aligned contacts and minimum geometry junctions, for reduced capacitance. The technology has been demonstrated by the fabrication of a CMOS VLSI memory with nearly half a million 1µm transistors.

Process technology for submicron BiCMOS VLSI

Submicron BiCMOS is rapidly emerging as the technology of choice for many high-performance VLSI memory and logic applications. Compared to their CMOS counterparts, BiCMOS circuits can be up to a factor of two faster for the same level of technology maturity. Access times below 10 ns are being reported for 0.8- mu m BiCMOS ECL (emitter-coupled logic) input/output 256 K and 1 Mb SRAMs, and 100 K gate arrays are capable of 100-MHz clock rates. Recent advances in submicron BiCMOS device structures and process technology that have made these previously unobtainable performance-density levels possible are reviewed.<<ETX>>

Submicron BiCMOS well design for optimum circuit performance

The optimization of a submicron BiCMOS well design is described. The use of buried layers, a thin intrinsic epi layer, and a double n-well implant creates steeply graded well profiles which result in improved circuit performance due to lower diode capacitance. High contact resistance to the buried n+ layer is avoided by using a novel polysilicon plug contact process which also eliminates lateral n+ diffusion, enabling the base-to-collector design rule to be shrunk by more than 25%.<<ETX>>

BiCMOS Process Technology

For high performance LSI and VLSI digital circuit applications, BiCMOS technology has become predominantly driven from a CMOS processing base. The principle reason for this is that LSI and VLSI digital BiCMOS circuits tend to be CMOS-intensive because of power dissipation limitations (for example, high density ECL I/O SRAMs and gate arrays). The CMOS-intensive nature of these circuits requires a process technology that will result in the highest possible CMOS performance. Consequently, BiCMOS fabrication technology tends to be CMOSbased, and the process steps needed to realize a high performance bipolar device are usually merged with a core CMOS process flow [3.1,3.2,3.3]. In the case of analog BiCMOS, the increasing demand to have on-board digital logic integration has also resulted in these processes being CMOS-oriented.

A 0.5- mu m BiCMOS technology for logic and 4 Mbit-class SRAMs

The authors describe a 0.5- mu m BiCMOS technology for high-performance logic and SRAMs (static RAMs) which is capable of supporting 5-V hot-carrier-hard circuit designs. In these designs the maximum drain-to-source voltage across a 0.5- mu m NMOS device is restricted to 4 V to ensure hot carrier reliability using 12-nm gate oxide. However, for the bipolar device, isolation and longer channel MOS devices, the process is required to support 5 V. For a 5-V supply voltage, the capacitive load drive factor for a BiCMOS NAND gate is 160 ps/pF, which is 30% smaller than the load drive factor for the same basic design gate built using an 0.8- mu m process with 20-nm gate oxide. The authors also discuss how a vertical NMOS driver transistor and a polysilicon PMOS load device are integrated into the 0.5- mu m BiCMOS process. The addition of these components permits a 23- mu m/sup 2/ stacked 6-T CMOS SRAM cell to be realized, suitable for 4-Mb-class BiCMOS SRAMs.<<ETX>>