Hilde Tielens

Atomic Layer Deposition of Gd-Doped HfO2 Thin Films

Gd x Hf 1-x O y thin films were deposited by atomic layer deposition (ALD) using tris(isopropyl-cyclopentadienyl) gadolinium [Gd( i PrCp) 3 ] and HfCl 4 in combination with H 2 0 as an oxidizer. Growth curves showed a nearly ideal ALD behavior. The growth per individual Gd( i PrCp) 3 /H 2 O or HfCl 4 /H 2 O cycle was 0.55 A, independent of the Gd/(Gd + Hf) composition x in the studied range. This indicates that the amount of HfO 2 deposited during a HfCl 4 /H 2 O cycle was essentially identical to the amount of Gd 2 O 3 deposited during a Gd( i PrCp) 3 /H 2 O cycle, assuming identical atomic densities of the films independent of composition. The crystallization of Gd x Hf 1-x O y , with Gd/(Gd + Hf) contents x between 7 and 30% was studied. Films with x ≳ 10% crystallized into a cubic/tetragonal HfO 2 -like phase during spike or laser annealing up to 1300°C, demonstrating that the cubic/tetragonal phase is thermally stable in this temperature range. A maximum dielectric constant of K ~ 36 was found for a Gd/(Gd + Hf) concentration of x ~ 11%.

Ozone-Based Metal Oxide Atomic Layer Deposition: Impact of N2 / O2 Supply Ratio in Ozone Generation

The 0 2 /N 2 flow ratio during O 3 generation by dielectric barrier discharge has a large impact on the atomic layer deposition (ALD) of metal oxides in a hot wall ALD reactor. For HfO 2 ALD using HfCl 4 as a metal precursor, a higher growth per cycle and a broader ALD temperature window are obtained when N 2 is added to the O 2 supply of the O 3 generation. A positive impact of N 2 in the 0 3 generation is also observed for ZrO 2 and La 2 O 3 ALD. A negative impact is observed for Al 2 O 3 ALD: The Al 2 O 3 thickness is reduced for those conditions for O 3 where Hf0 2 ALD is enhanced.

Process-improved RRAM cell performance and reliability and paving the way for manufacturability and scalability for high density memory application

Here for the first time we discuss RRAM cell performance and reliability through process improvement. Excellent post-cycling (106) retention and post-bake retention and endurance have been achieved for the optimized process conditions. The optimized RRAM cells show potential for manufacturability and scalability for high density memory application.

Effective Work Function Engineering for Aggressively Scaled Planar and Multi-Gate Fin Field-Effect Transistor-Based Devices with High-k Last Replacement Metal Gate Technology

This work reports on aggressively scaled replacement metal gate, high-k last devices (RMG-HKL), exploring several options for effective work function (EWF) engineering, and targeting logic high-performance and low-power applications. Tight low-threshold voltage (VT) distributions for scaled NMOS devices are obtained by controlled TiN/TiAl-alloying, either by using RF-physical vapor deposition (RF-PVD) or atomic layer deposition (ALD) for TiN growth. The first technique allows optimization of the TiAl/TiN thicknesses at the bottom of gate trenches while maximizing the space to be filled with a low-resistance metal; using ALD minimizes the occurrence of preferential paths, at gate sidewalls, for Al diffusion into the high-k dielectric, reducing gate leakage (JG). For multi-gate fin field-effect transistors (FinFETs) which require smaller EWF shifts from mid-gap for low-VT: 1) conformal, lower-JG ALD-TiN/TaSiAl; and 2) Al-rich ALD-TiN by controlled Al diffusion from the fill-metal are demonstrated to be promising candidates. Comparable bias temperature instability (BTI), improved noise behavior, and slightly reduced equivalent oxide thickness (EOT) are measured on Al-rich EWF-metal stacks.

Process control & integration options of RMG technology for aggressively scaled devices

We report on aggressively scaled RMG-HKL devices, with tight low-V_T distributions [σ(V_Tsat) ~ 29mV (PMOS), ~ 49mV (NMOS) at L_gate~35nm] achieved through controlled EWF-metal alloying for NMOS, and providing an in-depth overview of its enabling features: 1) physical mechanisms, model supported by TCAD simulations and analysis techniques such as TEM, EDS; 2) process optimizations implementation: oxygen sources reduction, control of RF-PVD TiAl/TiN ratio and reduced H_gate, also impacting stress induced in the channel. Additional key features: 1) Al vs. W as fill-metal, with careful liner/barrier materials selection and tuning yielding well-behaved devices with tight R_gate distributions down to L_gate~20nm, and enabling both PMOS and NMOS low-VT values for high aspect-ratio gates (H_gate~60nm, L_gate≥30nm); 2) wet-etch vs. siconi clean for dummy-dielectric removal, with HfO₂ post-deposition N₂-anneal resulting in substantial BTI improvement without EOT or low-field/peak mobility penalty, and good noise response.

Impact of thermal treatment upon morphology and crystallinity of strontium titanate films deposited by atomic layer deposition

Strontium titanate (STO) is a dielectric with a cubic perovskite type structure and of increasing interest for microelectronics, especially in the metal-insulator-metal (MIM) capacitors due to its high dielectric constant. The dielectric constant of the STO films and consequently the performance of the MIM capacitors appear to be strongly influenced by the process conditions. In this work the authors report on the influence of various thermal treatments upon the crystallinity and morphology of strontium titanate crystals. The influence of spike, laser, or rapid thermal anneals on the morphology with respect to grain size and topography of the crystalline stoichiometric STO films is studied. Also, the use of a stack containing a Sr-rich STO (62% Sr) bottom seed layer and a stoichiometric STO top layer in combination with a thermal treatment was found to affect the microstructure of the STO film. A comparison of the electrical properties for various thermal treatments has been made.

Impact of precursor chemistry on atomic layer deposition of lutetium aluminates

Rare earth-based oxides are of interest for their potential application in future logic high-performance technologies where Germanium is the channel material. In addition, their aluminates are considered as promising high-k dielectrics for nonvolatile memory technologies. However, it has been found that the dielectric quality of these materials is highly dependent on the method of preparation. The authors have therefore examined the atomic layer deposition (ALD) of LuxAl2−xO3 layers by means of Tris(isopropyl cyclopentadienyl) Lutetium (Lu(iPrCp)3), Tris(diethyl-amido)aluminum and H2O or O3 in a nanolaminate approach. This manuscript covers the impact of the oxidizer on both the ALD process characteristics and LuxAl2−xO3 layer properties. Because of the hygroscopic nature of rare earth oxides, the O3-based ALD of LuxAl2−xO3 is well controlled compared to the H2O-based process. On the other hand, LuxAl2−xO3 dielectrics grown with H2O as the oxidizer show better electrical properties in terms of Equivalent ...

Development and evaluation of a-SiC:H films using a dimethylsilacyclopentane precursor as a low-k Cu capping layer

Scaling of the Cu interconnect structures requires Cu capping layers with an increasingly lower dielectric constant (K) that still have adequate Cu and moisture barrier properties. In this work, we study the plasma enhanced chemical vapour (PE-CVD) deposition of amorphous silicon carbide films using dimethyl silacyclopentane (DMSCP) as a precursor, resulting in the incorporation of Si-(CH2)n-Si bridges. The effect of process parameters on film characteristics like K, mass density (p), and leakage behaviour is investigated, as well as their relation with the chemical bonding structure. Finally, Cu barrier properties and hermeticity are evaluated.

Fundamental study of atomic layer deposition in and on porous low-k films

Atomic layer deposition is a promising technique to deposit conformal, nm-thin metal barriers in high aspect ratio trenches. However, exactly because of its excellent conformality, the deposition can also occur inside the nanopores of the most advanced low-k materials. In this work, the mechanisms of atomic layer deposition on and in low-k, porous dielectric films were studied, using HfO2 as a test material. Exhaustive analyses showed firstly that the HfCl4 precursor penetrated uniformly in the pores throughout a 44 nm low-k film. Secondly it is shown that the pores were sealed as function of precursor size, i.e. there are conditions where the pores became inaccessible for HfCl4, while the - smaller - H2O molecules could still penetrate the pores. From these analyses a deposition model was proposed.

W versus Co--Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22 nm Technology Nodes

In this work we provide a comprehensive evaluation of a novel, low-resistance Co–Al alloy vs W to fill aggressively scaled gates with high aspect-ratios [gate height (Hgate) ~50–60 nm, gate length (Lgate) ≥20–25 nm]. We demonstrate that, with careful liner/barrier materials selection and tuning, well-behaved devices are obtained, showing: tight gate resistance (Rgate) distributions down to Lgate~20 nm, low threshold voltage (VT) values, comparable DC and bias temperature instability (BTI) behavior, and improved RF response. The impact of fill-metals intrinsic stress, including the presence of occasional voids in narrow W-gates, on devices fabrication and performance is also explored.