Mark Raymond

Optical metrology of Ni and NiSi thin films used in the self-aligned silicidation process

The thickness-dependent optical properties of nickel metal and nickel monosilicide (NiSi) thin films, used for self-aligned silicidation process, were characterized using spectroscopic ellipsometry. The thickness-dependent complex dielectric function of nickel metal films is shown to be correlated with the change in Drude free electron relaxation time. The change in relaxation time can be traced to the change in grain boundary (GB) reflection coefficient and grain size. A resistivity based model was used as the complementary method to the thickness-dependent optical model to trace the change in GB reflection coefficient and grain size. After silicidation, the complex dielectric function of NiSi films exhibit non-Drude behavior due to superimposition of interband absorptions arising at lower frequencies. The Optical models of the complete film stack were refined using x-ray photoelectron spectroscopy, Rutherford backscattered spectroscopy, and x-ray reflectivity (XRR).

A 7nm FinFET technology featuring EUV patterning and dual strained high mobility channels

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

Thickness Measurement of Thin‐metal Films by Optical Metrology

Spectroscopic ellipsometry (SE) and resistivity measurements were used to characterize Nickel‐metal films used for self‐aligned silicidation process. Variable angle spectroscopic ellipsometer (VASE) in the VUV range of wavelengths was used to measure the thickness and optical properties of Nickel films. The thickness‐dependent optical properties of thin‐metal films are shown to be correlated to the change in electron relaxation time and resistivity. The change in electron relaxation time and resistivity can be traced to the change in grain boundary reflection coefficient and grain size. X‐ray photoelectron spectroscopy (XPS) data aided with sputtering is used to show the evidence of the various stack layers that would be used in the VASE modeling. X‐ray reflectivity (XRR) and Rutherford backscattered spectroscopy (RBS) measurements on thin‐metal films were performed to complement the thickness measurements made with SE.

Tungsten and cobalt metallization: A material study for MOL local interconnects

Middle-of-the-line (MOL) interconnect and contact resistances represent significant impacts to high-end IC performance at ≤ 10 nm nodes. CVD W-based metallization has been used for all nodes since the inception of damascene. However, it is now being severely challenged due to limited scaling of the traditional PVD Ti/CVD TiN barrier and ALD nucleation layers. This study reports the use of alternate barriers, along with metal-to-metal contact interface cleans, to reduce contact resistance for W-based MOL metallization. As well, we report the first use of Co metal for MOL contacts and local interconnects, with successful integration below a Cu BEOL dual damascene V0/M1 module. Metal line resistances are compared among the various options, and the challenges with each option are highlighted.

Analysis of parasitic resistance in double gate FinFETs with different fin lengths

A significant increase in parasitic resistance (R<inf>PARA</inf>) fluctuation is observed when S/D length is getting smaller than the characteristic length (L<inf>TRANS</inf>). Resistance change evaluated on double gate finFETs with various fin lengths shows an excellent agreement between the experimental data and the analytical model. Further R<inf>PARA</inf> fluctuation improvement can be realized by optimizing the L<inf>TRANS</inf>.

Ti and NiPt/Ti liner silicide contacts for advanced technologies

We discuss the transition to Ti based silicides for source-drain (SD) contacts for 3D FinFET devices starting from the 14nm node & beyond. Reductions in n-FET & p-FET contact resistances are reported with the optimization of metallization process & dopant concentrations. The optimization of SiGe epitaxy and addition of a thin interfacial NiPt(10%) are found to significantly improve p-FET contact performance.

Specific contact resistivity of n-type Si and Ge M-S and M-I-S contacts

We have theoretically investigated the specific contact resistivity of n-type Si and Ge metal-insulator-semiconductor contacts with various insulating oxides. We have found a significant reduction of the contact resistivity for both Si and Ge with an insertion of insulators at low and moderate donor doping levels. However, at the higher doping levels (>1020 cmu-3), the reduction of the contact resistivity is negligible and the contact resistivity increases as the insulator thickness increase. Thus, we have shown that the lowest possible contact resistivity can be achieved with the metal-semiconductor contact with highest possible activated doping density.

Sub-

We report record low 8.4 × 10^-10 Ω-cm² n-type S/D contact resistivity with laser-induced solid/liquid phase epitaxy of Si:P inside nano-scale contact trenches. Significant reduction of device resistance and resultant great gain of drain current has been demonstrated in scaled n-FinFETs with a contact length of 20 nm.

10^{-9}~\Omega

In this paper, a study on MOL (middle-of-the-line) RC performance and optimization of MOL resistance at both source/drain contact and local interconnect level at 7 nm node is presented. We focus on the device delay from 10 nm node to 7 nm node using a single stage driver circuit. The device delay is calculated based on a real 10 nm FINFET device. Then the result is compared with a shrunk version of the circuit at the 7 nm dimension. Therefore, using this model the impact of the MOL on the circuit performance can be determined. By using a liner-free W (tungsten) metallization at source drain contact level and Co (cobalt) or Ru (ruthenium) metallization in the MOL local interconnect level, a 45% reduction in MOL resistance was obtained which is crucial to achieve a better 7 nm MOL performance over the 10 nm node.

-cm2 n-Type Contact Resistivity for FinFET Technology

Low Ge content SiGe-based CMOS FinFET is one of the promising technologies [1-2] offering solutions for both high performance and low power applications. In this paper, we established a competitive SiGe-based CMOS FinFET baseline and examined various elements for high performance offering. The performance elements in gate stack, channel doping, contact resistance, and junction have been explored to provide a cumulative 20% / 25% (n/pFET) performance enhancement. These elements provide a viable path towards performance enhancement for future technology nodes.