Hiroki Shirai

A novel cylinder-type MIM capacitor in porous low-k film (CAPL) for embedded DRAM with advanced CMOS logics

A novel cylinder-type metal-insulator-metal (MIM) capacitor in porous low-k film (CAPL) is proposed for embedded DRAMs (eDRAMs). The CAPL removes long bypass-contacts (BCT) with high resistance, which have been used to connect transistors with Cu interconnects by way of the MIM capacitor layer. A key technical challenge for the CAPL integration is control of pore structure in the low-k film to avoid metal contamination during the gas-phase deposition of the MIM electrode (BE) on the porous low-k film. A molecular-pore-stack (MPS) SiOCH film (k=2.5) with very small pores (0.4 nm-diameter) is found to be the best candidate for the CAPL structure, applicable to eDRAM with high performance logics for 28 nm-node and beyond.

Overview and Future Challenges eDRAM Technologies

This paper presents stacked-capacitor type eDRAM (embedded DRAM) device technologies enabling high-speed random access and low-power operation. Technology trend from 180nm to 55nm generation and future challenges will be described. We have focused onto wide-band data streaming application field such as servers, networks and graphics. For these applications, full compatibility with pure CMOS is essential as they require leading-edge CMOS performance and scaled-down design-rules. The key solution is low temperature stacked-capacitor formation below the thermal budget limitation of leading-edge CMOS Trs. of each generation. Technology Roadmap Figure 1 shows cell size trend from 180nm-55nm generation together with the DRAM cell cross-sectional view. A.(180nm)Co-salicide formation in DRAM cell area and MIS(Metal-Insulator-Silicon) capacitor Co-salicide formation in DRAM cell area had been the essential technology for boosting eDRAM cell Tr performance and minimizing embedded DRAM fabrication cost [1]. MIS capacitor, consisting of TiN&poly-silicon/Ta2O5/hemispherical grained (HSG) silicon, had achieved good C-V & I-V characteristics in this generation. B.(150nm) MIM(Metal-Insulator-Metal) capacitor Since 150nm-node, thermal budget limitation of leading-edge CMOS Trs. had decreased to below 600deg C (Fig.2). However, MIS capacitor formation requires annealing at 800deg C to suppress the depletion in the HSG bottom electrode. MIM capacitor technology was developed to solve this issue, keeping compatibility of logic Trs. performance. MIM capacitor, consisting of W-TiN/Ta2O5/TiN, can be formed below 500deg C [2]. MIM capacitor also achieved excellent capacitance characteristic with no dependence on applied voltage, as well as well-suppressed leakage current. C.(130nm)FMD(Full-Metal-DRAM) technology FMD technology, featuring that major components of DRAM cell are formed of metallic material, drastically reduced parasitic resistances [3]. Cell Trs. SD silicidation and W-plug metal capacitor contacts or bit line contacts have achieved 1/1000 resistance reduction compared with conventional cell technology. From 130nm-node, cell structure has been changed to COB(Capacitor Over Bitline) from CUB(Capacitor Under Bitline) for ensuring cell capacitance in spite of cell size reduction. And wiring metal material has been changed to copper from aluminum. Logic CMOS performance improvement by scaling and eDRAM cell parasitic resistance reduction by FMD enable over 450MHz random access operation @1.2V. D.(90nm)MIM2 introducing ALD(Atomic-Layer-Deposition) ZrO2 dielectric With reduction of cell size, it’s hard to keep sufficient cell capacitance using Ta2O5 dielectric even for COB structure because of leakage issue. At Teq(equivalent oxide thickness) = 1.5nm, leakage current @100deg C exceeds our criteria. Therefore, we have developed new MIM dielectric material with which leakage current characteristic has very small dependence on temperature. Several high-k materials were investigated, such as HfO2 or Al2O3. Finally, we have chosen ALD ZrO2 dielectric. Figure 3 shows excellent leakage current characteristic of ZrO2 compared with other high-k materials @125deg C. We named this W-TiN/ZrO2/TiN structure capacitor MIM2. This MIM2 can be formed below 400deg C so that it dose not affect logic CMOS performance at 90nm-node and beyond. The compatibility of pure logic Trs. is shown in Fig.4. Future Challenges A.(55nm) High-k Gate-dielectric Technology Beyond 55nm-node, as gate oxide thickness is scaled down to improve CMOS performance, Tr. leakage component such as gate leakage or GIDL(Gate-Induced Drain Leakage) becomes an issue especially for low standby-power application. High-k gate-dielectric is developed to solve this conflicting issue, reducing leakage and scaling-down gate oxide simultaneously. This high-k gate dielectric technology exploiting work function modulation, can achieve appropriate Vth with low channel dopant concentration [4]. Low channel doping realizes several desirable characteristics, such as higher mobility, GIDL reduction, device variability reduction, and gamma coefficient reduction. DRAM Cell Trs. are also well-benefited from these high-k gate Tr. characteristics. For example, figure 5 compares Vth-Vsub of cell Tr. with and without high-k, showing that gamma coefficient is reduced by using high-k Tr. B.(45nm and beyond) Technical Issues Scaled-down stacked type eDRAM has several issues, such as limitation of thermal budget, increase of contact resistance and capacitance reduction. MIM(MIM2) and FMD Technologies have solved these issues. We believe these solutions are extendible to 45nm-node. For 32nm-node and beyond, new materials or new structures may be required. Acknowledgment The authors appreciate S. Kishi, Y. Yamagata and T. Kuwata for their advices and encouragements. We also thank T. Kitamura and Y. Aoki for their technical support. Extended Abstracts of the 2006 International Conference on Solid State Devices and Materials, Yokohama, 2006, -130F-2-1 (Invited) pp. 130-131

Concentration dependence of cation-induced electrohydrodynamic flow passing through an anion exchange membrane

Electrohydrodynamic (EHD) flow is a type of liquid flow driven by an external electric force. In electrolyte solutions, anions and cations usually interact with each other to maintain electroneutrality. Under such a condition, it is difficult to drive a liquid flow by applying electric potentials on the order of 1 V; at least a few tens of volts is required to generate EHD flows, which may not be preferable for aqueous solutions. In this study, we propose a novel method of generating a liquid flow through a channel with cross-sectional dimensions of 1 × 1 mm2, which is placed in an ion exchange membrane to separate the cation and anion transport pathways. When the optimized design of the experimental apparatus was used, EHD flows were successfully generated in aqueous solutions by applying a relatively low electric potential of 2.2 V, and the flow velocity was measured over a wide range of electrolyte concentrations by particle image velocimetry. It was found that high concentration gradients caused the rapid discharge of ions passing through the channel and contributed to achieving a flow speed on the order of 1 mm/s. EHD flows were also theoretically explained using the Navier–Stokes equations to model an ion-drag flow driven by nonequilibrium ion transport in external electric fields. This flow generation method is practical only when ion transport pathways are well controlled and effectively rectified. The present findings will lead to the development of a promising technology to control liquid flows in multiscale fluidic channels.

Basic Performance of a Logic Intellectual Property Compatible Embedded Dynamic Random Access Memory with Cylinder Capacitors in Low-k/Cu Back End on the Line Layers

We have confirmed the basic performance of a new logic intellectual property (IP) compatible (LIC) embedded dynamic random access memory (eDRAM) with cylinder capacitors in the low-k/Cu back end on the line (BEOL) layers. The LIC-eDRAM reduces the contact (CT) height, or essentially the RC delays due to the parasitic component to the contact. By circuit simulation, a 28-nm-node LIC-eDRAM with the reduced CT height controls the logic delay with Δτd < 5% to that of 28-nm-node standard complementary metal oxide semiconductor (CMOS) logics, enabling us ensure the logic IP compatibility. This was confirmed also by a 40-nm-node LIC-eDRAM test-chip fabricated. The 40-nm-node inverter delays in the test-chip were controlled actually within Δτd < 5%, referred to those of a pure-CMOS logic LSI. Meanwhile the retention time of the DRAM macro was in the range of milliseconds, which has no difference to that of a conventional eDRAM with a capacitor-on-bitline (COB) structure. The LIC-eDRAM is one type of BEOL memory on standard CMOS devices, and is sustainable for widening eDRAM applications combined with a variety of leading-edge CMOS logic IPs, especially beyond 28-nm-nodes.

Performance Evaluation of a Logic-IP Compatible (LIC) Embedded DRAM with Cylinder Capacitors in Low-k/Cu BEOL Layers

Introduction Embedded DRAMs (eDRAMs) are attractive for realizing high bandwidth, low latency, and low power of the memory-logic interface with small cell size [1-2]. In the conventional “capacitor over bit-line (COB)” structure, cylinder capacitors for storage nodes are located between M1 and bit-lines, and bypass-contacts need to be added to the conventional contacts for connecting CMOS transistors to M1 (Fig.1). For deep scaling beyond 40 nm technology, higher cylinder capacitors are needed to keep the node capacitance (Cs) per each cell. This may lead to significant increase of the contacts (CT) height, parasitic resistance and capacitance, or even RC-delay of the logic parts in the eDRAM circuit. We have proposed a novel concept of the logic-IP compatible (LIC) eDRAM containing cylinder capacitors in low-k/Cu BEOL layers, and confirmed feasibility of the capacitor integration with low CT heights to keep compatibility with standard CMOS logic IPs [3]. The LIC-eDRAM is categorized as a “BEOL memory,” of which memory elements are located in interconnect layers such as MRAM [4] and ReRAM [5]. In this paper, we focus on the logic delays of the LIC-eDRAM referred to those of the pure CMOS logics obtained by the circuit simulation for 28nm-node in conjunction with the actual measurement for 40nm-node test-chips.