J. Kawahara

Highly reliable BEOL-transistor with oxygen-controlled InGaZnO and Gate/Drain offset design for high/low voltage bridging I/O operations

Reliability of BEOL-transistors with a wide-gap oxide semiconductor InGaZnO (IGZO) film, integrated on LSI Cu-interconnects, is intensively discussed in terms of application to on-chip bridging I/Os between low and high voltage interactive operations (Fig. 1). Oxygen control in the thin IGZO film was found to be important to stabilize the device characteristics. A conventional IGZO tends to contain deep-level donor-states, which cause temperature and bias instabilities. The oxygen control in IGZO reduces these deep donor-states to improve operation instability. A gate/drain offset structure effectively suppresses the hot-carrier generation, resulting in a stable operation at high Vd bias condition (∼20V). The oxygen-controlled IGZO and gate/drain offset structure are important for making the BEOL-transistors applicable to high/low voltage I/Os bridging.

A novel cylinder-type MIM capacitor in porous low-k film (CAPL) for embedded DRAM with advanced CMOS logics

A novel cylinder-type metal-insulator-metal (MIM) capacitor in porous low-k film (CAPL) is proposed for embedded DRAMs (eDRAMs). The CAPL removes long bypass-contacts (BCT) with high resistance, which have been used to connect transistors with Cu interconnects by way of the MIM capacitor layer. A key technical challenge for the CAPL integration is control of pore structure in the low-k film to avoid metal contamination during the gas-phase deposition of the MIM electrode (BE) on the porous low-k film. A molecular-pore-stack (MPS) SiOCH film (k=2.5) with very small pores (0.4 nm-diameter) is found to be the best candidate for the CAPL structure, applicable to eDRAM with high performance logics for 28 nm-node and beyond.

Robust low-k film with sub-nm pores and high carbon content for highly reliable Cu/low-k BEOL modules

Critical parameters of low-k films were defined to keep capacitance benefit and TDDB reliability in the scaling BEOL module, according to various analyses. In order to meet the criteria of high carbon content, low porosity with small pores, and high adhesion strength with less adhesion layer, precursor and process were designed for the SiOCH with k~2.5. The benefits in integration and reliability from the newly developed robust low-k film were verified through the trench-first integration of 80 nm-pitch BEOL modules.

RF performance upgrading of low-power 40nm-node CMOS devices by extremely low-resistance partially-thickened local (PTL)-interconnects

A new partially-thickened local (PTL)-interconnect structure with an extremely low resistance is developed for the 40 nm-node low-power CMOS device to boost the RF performance. The PTL-interconnect is featured by the Cu dual-damascene (DD) interconnect combined with the slit-contact (SLICT) in the low-k pre-metal-dielectrics (PMD, k=3.1), accomplishing 50% reduction in the resistance of metal-1 (M1), and the contact resistance between M1 and the gate silicide-interconnect also decreased remarkably. The maximum oscillation frequency (fmax), which is influenced strongly by the effective gate resistance as an input signal port, increased 30% referred to that with conventional W-pillar contacts in the SiO2-PMD. The low-resistance PTL-interconnect backed with the Cu-DD SLICT in the low-k PMD is essential for low-power RF/mixed-signal SoCs.

RF performance boosting for 40nm-node CMOS device by low-k/Cu dual damascene contact

To enhance RF performance, low-k/Cu dual-damascene (DD) contact is implemented into 40 nm-node CMOS devices for the first time. The Cu DD contact in reliable double-layered low-k films of silica-carbon composite (SCC, k=3.1) and SiOCH (k=3.1) boosts the cut-off frequency (fT) and the maximum oscillation frequency (fmax) by 8.0 % and 10.5% referred to those of the conventional SiO2/W-plug structure, respectively. The low-k/Cu-DD contact structure becomes effective to reduce the parasitic factors in the scaled-down 40 nm-node more than the 55 nm-node reported. The contact resistance and the parasitic capacitance (Cgs) are reduced by 80% (one-fifth) and 17% referred to those of the conventional SiO2/W-plug structure, respectively. The low-k/Cu DD contact is essential to scaled-down CMOS devices for RF/ubiquitous applications.

A simple model-base prediction method for delamination failures in Low-k/cu interconnects with flip chip packages

A model-base prediction method is proposed for delamination/cracking failures in Low-k/Cu interconnects with Pb-free FCBGA (Flip Chip-Ball Grid Array). The low-k failure under the solder bump, so called as a white bump (WB) failure, is caused by large thermal stress to a brittle low-k film during the cooling process from high reflow temperature for the Pb-free solder. Based on failure analysis using several low-k films and several packaging materials/structures, we found that occurrence of the WB failure is able to be predicted by a simple evaluation function of the simulated strain energy and a critical energy release rate of crack, which is defined by the fracture toughness and the adhesion-strength of the low-k film. According to this method, we can lead a preliminary design guideline on the bump pitch/structure or the interposer material/structure toward no WE failure quickly.

Control of plasma polymerization reaction for the 2 nd generation molecular_pore_stack (MPS) SiOCH film with high deposition rate

To reducing BEOL fabrication cost for 28/20nm-nodes, high-speed process of the low-k deposition is needed under limited equipment investment. By using a standard plasma-CVD equipment with no post-cure process, we have developed high speed deposition technique for a molecular_pore_stack (MPS) SiOCH film from single precursor, which has a hexagonal-silica-ring with hydrocarbon side-chains. Here, the plasma polymerization reaction of the precursors was enhanced simply by controlling the RF power and the gas chemistry with additive gas, which was dissociated itself to increase active charge flux in the plasma. The deposition rate was doubled while keeping the film properties unchanged with the sub-nanometer-size porous structure. No change in the RC performance of the Cu interconnect was observed by using the new MPS film with the high deposition rate. The mechanical properties also were preserved to keep chip-packaging-interaction tolerance.

Performance Evaluation of a Logic-IP Compatible (LIC) Embedded DRAM with Cylinder Capacitors in Low-k/Cu BEOL Layers

Introduction Embedded DRAMs (eDRAMs) are attractive for realizing high bandwidth, low latency, and low power of the memory-logic interface with small cell size [1-2]. In the conventional “capacitor over bit-line (COB)” structure, cylinder capacitors for storage nodes are located between M1 and bit-lines, and bypass-contacts need to be added to the conventional contacts for connecting CMOS transistors to M1 (Fig.1). For deep scaling beyond 40 nm technology, higher cylinder capacitors are needed to keep the node capacitance (Cs) per each cell. This may lead to significant increase of the contacts (CT) height, parasitic resistance and capacitance, or even RC-delay of the logic parts in the eDRAM circuit. We have proposed a novel concept of the logic-IP compatible (LIC) eDRAM containing cylinder capacitors in low-k/Cu BEOL layers, and confirmed feasibility of the capacitor integration with low CT heights to keep compatibility with standard CMOS logic IPs [3]. The LIC-eDRAM is categorized as a “BEOL memory,” of which memory elements are located in interconnect layers such as MRAM [4] and ReRAM [5]. In this paper, we focus on the logic delays of the LIC-eDRAM referred to those of the pure CMOS logics obtained by the circuit simulation for 28nm-node in conjunction with the actual measurement for 40nm-node test-chips.

Effect of Via-Profile on the Via Reliability in Scaled-down Low-k/Cu Interconnects

Introduction In order to reduce power consumption and signal propagation delay in 40 nm-node LSI and beyond, porous low-k films with k-value (dielectric constant) less than 2.6 is introduced into Cu dual damascene interconnects (DDIs). Introduction of the porous low-k faces a big challenge to suppress process-induced damages, or increasing the k-value, during the DD integration process such as etching, metallization, and CMP . From a viewpoint of the reliability, the DD via-profile in low-k films has a critical impact especially on the stress induced voiding (SiV). For example, it is reported that the SiV was promoted by the fenced-vias . In this study, we investigate the effect of the via profile on SiV in the full-low-k/Cu DDIs. Three types of the non-fenced vias are prepared; i.e., (1) shallow-tapered, (2) stepped, and (3) deep-tapered vias with the via-bottom diameter of 70nm. It is found that the shallow-tapered and the stepped vias achieve high endurance against the SiV due to relaxing the stress gradient at the via bottom.