Ippei Kume

Improvement of Uniformity and Reliability of Scaled-Down Cu Interconnects with Carbon-Rich Low-k Films

Highly selective dry-etching processes are developed for conventional via-first (VF) pattering sequences to fabricate reliable Cu dual-damascene interconnects (DDI) in carbon-rich low-k films, such as a molecular-pore-stack (MPS) SiOCH film (k = 2.55). The carbon-rich MPS film, which had excellent endurance against plasma-processes, acted as etching stopper during hard-mask (HM)-etching on it, and the high selectivity of trench-HM etching reduced variability of over-etching depth in the MPS film. This effect reduced variability in trench-depth in the MPS film, or interconnect characteristics such as capacitance–resistance (C–R) time delay. The via yield and reliability were influenced also by via-etch selectivity of MPS against SiCN cap underlain. We found that the SiCN thickness remained after the via etch should be greater than 10 nm to prevent Cu from oxidation by O2 ashing step followed. Chemical-reaction-enhanced gas chemistry in N2–CFX–Ar system, i.e., high N2/Ar ratio under limited CFX supply, increased the etching selectivity of MPS to keep enough thickness of SiCN. Early-failure-mode in electro-migration test was suppressed by the high selective via-etch. Precise selectivity control for robust carbon-rich low-k films was very important to achieve the low variability and high reliability of scaled-down Cu interconnects.

Precise Taper-Angle-Control of Via Holes for Reliable Scaled-Down Low-

A highly reliable Cu dual-damascene interconnect (DDI) was developed in a molecular-pore-stack (MPS) SiOCH film (k = 2.5) with precise taper angle control at the top and bottom of via holes. The durable MPS film with the carbon-rich composition revealed no reliability deterioration in the time-dependent dielectric breakdown (TDDB) between the 140-nm pitched lines. The stres-induced voiding (SiV) was suppressed completely by precise taper angle control both at the top and bottom of via holes. A shallow-tapered via and a stepped via, in which these top taper angles (θtop) were greater than 45° while keeping the bottom angle (θbtm) steep at approximately 90°, improved the SiV reliability referred to a deep-tapered via with θbtm90°. Finite element method (FEM) simulation well explains the dependence of SiV reliability on both θtop and θbtm; the increment of θtop reduces the stress gradient under the via, while the decrease in θbtm enlarges the stress gradient. Namely, the precise taper angle control of both the top and bottom via is very important to improve the SiV reliability, and the shallow-tapered and the stepped vias in the MPS film were confirmed to achieve high endurance against the SiV due to relaxation of the stress gradient under the via.

k

Highly reliable metal–insulator–metal (MIM) capacitor with ultra-thin SiN dielectrics is developed on the surface-controlled bottom electrode in nanometer-scales. Coverage of the TiN bottom electrode with a Ta thin layer achieves smooth surface. In addition, this electrode structure exhibits excellent etching controllability even for the MIM with the ultra-thin SiN dielectrics. The smooth surface of the Ta/TiN stacked electrode improves the dielectric characteristics such as leakage, breakdown and time-dependent dielectric breakdown (TDDB) reliability in the MIM capacitors, integrated into Cu dual-damascene interconnects (DDIs). As a result, the SiN-MIM with the Ta/TiN bottom electrode achieves high capacitance of 7 fF/µm2 as well as high reliabilities, which are 20% higher breakdown field and 6000 times longer TDDB lifetime than that without Ta-insertion. These values guarantee the high performance operation for more than 10 years under the environment at 85 °C.

/Cu Interconnects

Low-temperature plasma-oxidation process of ultra-thin PVD-Ta is developed to fabricate MIM capacitors with high-k TaO dielectric through the current Cu-BEOL process. We found that controlling both the oxidation process and micro-structure of the initial Ta to be oxidized is a key to achieve high-quality TaO dielectrics. Laminated TiN/Ta/TiN bottom electrode with a flat surface in nano-scale contributes to high reliability. The integrated TaO-MIM capacitor in the Cu-BEOL achieves high breakdown voltage of 10 V with high capacitance of 13 fF/¿m2, and the TDDB lifetime at 85 °C exceeds 10 years at less than 4 V (2 MV/cm).

Surface Control of Bottom Electrode in Ultra-Thin SiN Metal–Insulator–Metal Decoupling Capacitors for High Speed Processors

A model-base prediction method is proposed for delamination/cracking failures in Low-k/Cu interconnects with Pb-free FCBGA (Flip Chip-Ball Grid Array). The low-k failure under the solder bump, so called as a white bump (WB) failure, is caused by large thermal stress to a brittle low-k film during the cooling process from high reflow temperature for the Pb-free solder. Based on failure analysis using several low-k films and several packaging materials/structures, we found that occurrence of the WB failure is able to be predicted by a simple evaluation function of the simulated strain energy and a critical energy release rate of crack, which is defined by the fracture toughness and the adhesion-strength of the low-k film. According to this method, we can lead a preliminary design guideline on the bump pitch/structure or the interposer material/structure toward no WE failure quickly.

Low-Temperature Plasma-Oxidation Process for Reliable Tantalum-Oxide (TaO) Decoupling Capacitors

We have confirmed the basic performance of a new logic intellectual property (IP) compatible (LIC) embedded dynamic random access memory (eDRAM) with cylinder capacitors in the low-k/Cu back end on the line (BEOL) layers. The LIC-eDRAM reduces the contact (CT) height, or essentially the RC delays due to the parasitic component to the contact. By circuit simulation, a 28-nm-node LIC-eDRAM with the reduced CT height controls the logic delay with Δτd < 5% to that of 28-nm-node standard complementary metal oxide semiconductor (CMOS) logics, enabling us ensure the logic IP compatibility. This was confirmed also by a 40-nm-node LIC-eDRAM test-chip fabricated. The 40-nm-node inverter delays in the test-chip were controlled actually within Δτd < 5%, referred to those of a pure-CMOS logic LSI. Meanwhile the retention time of the DRAM macro was in the range of milliseconds, which has no difference to that of a conventional eDRAM with a capacitor-on-bitline (COB) structure. The LIC-eDRAM is one type of BEOL memory on standard CMOS devices, and is sustainable for widening eDRAM applications combined with a variety of leading-edge CMOS logic IPs, especially beyond 28-nm-nodes.

A simple model-base prediction method for delamination failures in Low-k/cu interconnects with flip chip packages

Effects of post-etching treatment (PET) in trench patterning and re-sputtering in barrier metal sputtering on low-k/Cu interconnects were investigated for the low-k of Molecular Pore Stacking (MPS). Optimized combination of PET and re-sputtering reduces wiring capacitance by 5% due to well controlled profile, resulted from hardening effect of the exposed MPS at the trench bottom. The developed process sequence achieves 10 times loger EM lifetime and eliminates early failure mode in the TDDB test. Thus, the novel process, featuring PET and re-sputtering, contributes to highly reliability for 28 nm node CMOS and beyond.

Basic Performance of a Logic Intellectual Property Compatible Embedded Dynamic Random Access Memory with Cylinder Capacitors in Low-k/Cu Back End on the Line Layers

Introduction Embedded DRAMs (eDRAMs) are attractive for realizing high bandwidth, low latency, and low power of the memory-logic interface with small cell size [1-2]. In the conventional “capacitor over bit-line (COB)” structure, cylinder capacitors for storage nodes are located between M1 and bit-lines, and bypass-contacts need to be added to the conventional contacts for connecting CMOS transistors to M1 (Fig.1). For deep scaling beyond 40 nm technology, higher cylinder capacitors are needed to keep the node capacitance (Cs) per each cell. This may lead to significant increase of the contacts (CT) height, parasitic resistance and capacitance, or even RC-delay of the logic parts in the eDRAM circuit. We have proposed a novel concept of the logic-IP compatible (LIC) eDRAM containing cylinder capacitors in low-k/Cu BEOL layers, and confirmed feasibility of the capacitor integration with low CT heights to keep compatibility with standard CMOS logic IPs [3]. The LIC-eDRAM is categorized as a “BEOL memory,” of which memory elements are located in interconnect layers such as MRAM [4] and ReRAM [5]. In this paper, we focus on the logic delays of the LIC-eDRAM referred to those of the pure CMOS logics obtained by the circuit simulation for 28nm-node in conjunction with the actual measurement for 40nm-node test-chips.

Highly reliable molecular-pore-stacking (MPS)/Cu interconnects using novel post-etching treatment (PET) for 28 nm-node and beyond

The effects of postetching treatment (PET) using carbon-containing gas on molecular-pore-stacking (MPS)/Cu interconnects were investigated. By using this technology, a 5% reduction in wiring capacitance was obtained as a result of the hardening of exposed MPS at the trench bottom. Via-chain yield improvement was also confirmed as a result of eliminating of etching residues in via-holes. These results indicate that high production yield and reliability can be obtained by PET for 28-nm-node complementary metal oxide semiconductor (CMOS) devices and beyond.

Performance Evaluation of a Logic-IP Compatible (LIC) Embedded DRAM with Cylinder Capacitors in Low-k/Cu BEOL Layers

Impacts of k-value reduction on LSI performances are clarified quantitatively using 2M-gate net-list. Reduction in k-value from 3.0 to 2.5 for M2-M5 interconnect layers achieves 11%-drop in interconnect parasitic capacitance (Cint) and 8.4%-reduction in propagation delay (rd), which also shrinks the effective variability of zd to improve LSI operation margins. From a viewpoint of BEOL fabrication with k∼2.5, a carbon-rich porous SiOCH film has high tolerance to process-induced damages, resulting in lower Cint than that of an O-rich film with similar k-value. Sustainability to FCBGA packaging with Pb-free solder bumps is also confirmed for the multi-level interconnects with the C-rich porous SiOCH.