Kenichiro Hijioka

A Novel Variable Inductor Using a Bridge Circuit and Its Application to a 5–20 GHz Tunable LC-VCO

A novel variable inductor using a bridge circuit is proposed. Because of a bypass switch MOSFET placed at a balance point, the effect of the switch resistance which is a penalty of the variable inductance is suppressed and degradation of the Q factor is mitigated. A 10-20 GHz tunable LC-VCO core using this inductor was also fabricated. Because of the multi-stage variable inductor, 20 GHz operation having over 10 GHz continuous tuning range with phase noise of -103 to -84 dBc/Hz is achieved with only 5.2 to 7.1 mW power consumption. By using a 1/2 divider, a 5-20 GHz continuous tuning range is also obtained. The chip area is 1/10 smaller than that of conventional wide range LC-VCOs because of the miniature 3-D structure variable inductor. This variable inductor and the wide range LC-VCO are suit able for the clock generation of high-speed communication systems, multi-core processors, as well as low-power, low-cost wireless transceivers.

A 40Gb/s multi-data-rate CMOS transceiver chipset with SFI-5 interface for optical transmission systems

As 40Gb/s optical communication systems enter the commercial stage, the transceiver, which is a key component of these systems, requires lower power dissipation, a size reduction, and a wider frequency range to meet the requirements of several standards, such as OC-768/STM-256 (39.8Gb/s), OTU-3 (43.0Gb/s), and 4×10GbE-LANPHY (44.6Gb/s). 40Gb/s transceivers have already been reported in SiGe-based technology.However, they dissipate more than 10W in total and do not support 39.8-to-44.6Gb/s wide-range operations [1–2]. There have been recent reports on CMOS transceivers, but their speed performance is still less than 40Gb/s and their output signal suffers from large jitter [3–5]. In this paper, 40Gb/s SFI-5-compliant TX and RX chips in 65nm CMOS technology consume 2.8W each. This low power dissipation allows for a small and low-cost plastic BGA package. The TX has a full-rate clock architecture that is based on a 40GHz VCO, a 40Gb/s retiming D-FF, and 40GHz clock-distribution circuits that lead to a low jitter of 0.57psrms and 3.1pspp at 40Gb/s. A 40/20GHz clock-timing-adjustment circuit based on a phase interpolator is used to ensure wide-range error-free operations (BER ≪ 10−12) at 39.8 to 44.6Gb/s. A quadruple loop architecture is introduced in the CDR circuit of the RX, resulting in a 38Gb/s error-free operation (BER ≪ 10−12) at 231−1 PRBS with a low rms jitter of 210fs in the recovered clock.

A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems

A fully integrated 40 Gb/s transmitter and receiver chipset with SFI-5 interface is implemented in a 65 nm CMOS technology and mounted in a plastic BGA package. The transmitter chip provides good jitter performance with a 40 GHz full-rate clock architecture that alleviates pattern-dependent jitter and eliminates duty cycle dependence. The measured RMS jitter on the output is 570 fs to 900 fs over the range of 39.8 Gb/s to 44.6 Gb/s with a 231-1 PRBS pattern. The receiver chip operates over the range of 37 Gb/s to 41 Gb/s. The measured RMS jitter on the recovered clock is 359 fs to 450 fs. By taking advantage of CMOS technology, each chip achieves low power consumption of 2.8 W and full integration of SFI-5 functions, PRBS generators/error checkers, a DPSK precoder/decoder, and control interfaces in a 4.9 × 5.2 mm2 die.

Mechanical Property Control of Low-

The dielectric constant dependence of the mechanical strength and the adhesion strength is investigated using porosity-controlled low-k films, and a material parameter is clarified to suppress the chemical mechanical polishing (CMP)-related defects in Cu damascene interconnects. Mechanical strengths such as the modulus and hardness of low-k films decreased as the dielectric constant decreased. Adhesion energy between the low-k films and an upper hard-mask layer (HM) of PECVD-SiO2 strongly depends on the dielectric constant of low-k films, while adhesion energy between the low-k films and a lower etch stop layer (ES) of SiCN shows weak dependence. It was found that the adhesion energy between the upper SiO2 and the low-k film is a critical mechanical parameter for diminishing the CMP-related defects. Introducing a porous low-k film, methylsilsesquiazane (k=2.64), with high adhesion to the HM-SiO2, we successfully fabricated single damascene copper interconnects within an acceptable limit of CMP-related defects.

k

A low-power, small area quadrature 5GHz LC-VCO includes 20GHz oscillator and 1/4 divider has been fabricated using a miniature 3D solenoid shaped inductor in 90nm CMOS. Owing to a small area and a small magnetic energy of the 3D inductor, a chip area of 2597μm2 which is 1/10 of the reported smallest LC-VCOs and 2.8mW power consumption including the divider have been achieved without degrading a figure of merit (FOM). The phase noise was −103dBc/Hz (@1MHz offset) and the phase error was ≪1.3°. The PLL using this LC-VCO achieved 1.2ps rms jitter with the chip area as small as that of ring oscillators. This small area LC-VCO is suitable for low-power, low-cost wireless transceivers and high speed communication systems.

Dielectrics for Diminishing Chemical Mechanical Polishing (CMP)-Related Defects in Cu-Damascene Interconnects

Robust porous low-k/Cu interconnects have been developed for 65-nm-node ultralarge-scale integrations (ULSIs) with 180-nm/200-nm pitched lines and 100-nm diameter vias in a single damascene architecture. A porous plasma-enhanced chemical vapor deposition (PECVD)-SiOCH film (k=2.6) with subnanometer pores is introduced into the intermetal dielectrics on the interlayer dielectrics of a rigid PECVD-SiOCH film (k=2.9). This porous-on-rigid hybrid SiOCH structure achieves a 35% reduction in interline capacitance per grid in the 65-nm-node interconnect compared to that in a 90-nm-node interconnect with a fully rigid SiOCH. A via resistance of 9.7 /spl Omega/ was obtained in 100-nm diameter vias. Interconnect reliability, such as electromigration, and stress-induced voiding were retained with interface modification technologies. One of the key breakthroughs was a special liner technique to maintain dielectric reliability between the narrow-pitched lines. The porous surface on the trench-etched sidewall was covered with an ultrathin plasma-polymerized benzocyclobuten liner (k=2.7), thus enhancing interline time-dependent dielectric breakdown reliability. The introduction of a porous material and the control of the sidewall are essential for 65-nm-node and beyond scaled-down ULSIs to ensure high levels of reliability.

A low-power, small area quadrature LC-VCO using miniature 3D solenoid shaped inductor

Hybrid-type, Cu dual damascene interconnects (DDI) are fabricated in a porous organosilica film (k = 2.1) inserted between low-k films of hard-mask (HM) and etch-stop (ES) layers. Plasma-polymerized, divinyl siloxane bis-benzocyclobutene (p-BCB, k = 2.7) film, instead of SiCN film (k > 4), is selected for these HM and ES layers due to the low k-value as well as the high etch-stop property to the porous film. The line capacitance in the hybrid-type, Cu-DDI with BCB-HM and BCB-ES layers decreases 20% compared with that of the Cu-DDI with SiO/sub 2/-HM and SiCN-ES layers, achieving the effective dielectric constant (k/sub eff/) of 2.6. This new interconnect structure is a strong candidate for the 70 nm-node ULSIs.

Robust porous SiOCH/Cu interconnects with ultrathin sidewall protection liners

The impact of porous low-k films on circuit performance in GHz operation was investigated using high-speed circuits in 65 nm complementary metal oxide semiconductor (CMOS) LSI with 11-layered Cu dual damascene interconnects (DDIs). By introducing new non-porogen-type porous films, such as molecular-pore-stacking (MPS) SiOCH films, local low-k/Cu structures (M2–M5) with effective dielectric constants (Keff) of 3.1 and 2.9 were fabricated, and their circuit performances were compared to those with conventional local interconnects with Keff=3.4. The interline capacitance (Cint), measured using an LCR meter at ~100 kHz, was reduced by 12% from Keff=3.4 to 2.9. NAND-type ring oscillators (ROSCs), which were designed to have ~1.5 GHz oscillation, also achieved 12 and 10% reductions in signal delay and power consumption, respectively. A 2 GHz static random access memory (SRAM) with Keff=2.9 provides a 4% reduction in bit-line capacitance (M2), resulting in a 6% decrease in Vddmin, or eventually widening the SRAM operation margin. The porous low-k impact on GHz operation is demonstrated for the first time.

Cu dual damascene interconnects in porous organosilica film with organic hard-mask and etch-stop layers for 70 nm-node ULSIs

Low-loss oxide magnetic film of Ni–Zn ferrite (Ni0.5Zn0.5Fe2O4) is deposited by RF magnetron sputtering at a low temperature (300 °C), applicable for integration in advanced LSIs with Cu/low-k interconnects. To control the film microstructure, or its essential magnetic and electrical properties, (1) selection of a buffer layer as a diffusion barrier under the ferrite film and (2) control of the O2/Ar gas ratio in the sputtering chamber are key factors. A thin TaN buffer layer provides the Ni–Zn ferrite film with a highly preferential (311) orientation, resulting in high saturation magnetization. In addition, the thin TaN buffer has a sufficiently good barrier property to be practical for integration of the magnetic film into Cu/low-k interconnects. Oxygen addition to Ar sputtering gas realizes both high (311) crystallization and high resistivity (ρ=10 MΩ cm), which are essential for low-loss properties. Simulation of the on-chip inductor with the magnetic film suggests that the high-ρ magnetic film is suitable for high-efficiency on-chip inductors with GHz ranges.

Porous Low-

RF characteristics for sub-0.1μm MOSFETs such as fT, fmax and their variations are estimated from the DC and capacitance parameters. A new RF gate resistance model with a silicide-polysilicon interface resistance is a key factor to estimate the RF characteristics precisely. The variations of RF characteristics are also inferred from correlation coefficient between the RF parameters and the DC and capacitance parameters. This method is effective in monitoring RF characteristics and their variations for scaled-down, RF/mixed-signal circuits at the chip fabrication.