Hiroko Mori

Impact of Parasitic Bipolar Effect on Single-Event Upset in p-Type Metal–Oxide–Semiconductor Field Effect Transistor with Embedded SiGe

Accelerated neutron tests for soft error rate (SER) are carried out using unbalanced feedback-loop circuits fabricated by Si and embedded SiGe (eSiGe) processes. The contribution of the p-type metal–oxide–semiconductor field effect transistor (PMOS) to total SER is shown to substantially decrease in the eSiGe process. The characteristics of parasitic bipolar transistors in PMOSs with and without eSiGe are investigated using technology computer-aided design (TCAD) simulations. We find that the narrow band gap of SiGe causes an increase in the rate of electron flow from the well region (Si) to the source region (SiGe), leading to a decrease in the current gain of the parasitic bipolar transistor in PMOS with eSiGe. Our results indicate that eSiGe can be attributed to the suppression of the parasitic bipolar effect, resulting in a reduced contribution of PMOS to SER.

Detection Technique With Alpha-Tracking and Emissivity Comparison

We achieved accurate alpha emissivity measurement with the alpha-tracking technique by decreasing the background effect. It is possible to lower the detection limit of this technique to 4.9×10-2 alphas/kh-cm2 using a normal detector. We measured various large-scale integration materials using this technique.

Critical charge dependence of correlation of different neutron sources for soft error testing

We investigate the soft error rate (SER) deviations at sea level between calculation with JEDEC spectrum and measurements at acceleration test facilities. The ratio of SER calculated with the test facilitys spectrum to that with the JEDEC spectrum is provided as a function of critical charge. This ration is used for estimation of the SER at sea level from the SER measured at test facilities. Single event upset (SEU) cross-sections necessary in derivation of the SER ratio are given by a multi-scale (particle transport and 3D TCAD) Monte Carlo simulation. Finally, the SER ratio is verified through acceleration tests in three facilities.

Characterization of millisecond-anneal-induced defects in SiON and SiON/Si interface by gate current fluctuation measurement

In this paper, we have investigated bulk trap and interface trap density (Dit) caused by millisecond annealing (MSA) using gate current fluctuation (GCF) and charge pumping measurements. We show that the high energy flash lamp annealing (FLA) creates the GCF with a long duration time and it is critical issue to get a stable SRAM operation. FLA creates interface traps localized at the gate edge of MOSFET.

Generation of a New Interface State Associated with Ultrathin Gate Dielectrics/Silicon under Electric Stress

Applying charge pumping, we found a new narrow interface state that was generated above the intrinsic Fermi level in the silicon band gap in ultrathin gate dielectrics/silicon after hot-carrier injection. The width of the structure was about 0.1 eV. There was also a conventional defect structure, Pb0, in thin dielectrics. By investigating the correlation between the new structure and Pb0, the new structure was found not to originate from Pb0. Moreover, by position analysis, the new interface state was found to be generated apart from conventional Pb0. Thus, it is possible to obtain information on the new interface state separately. The atomic structure corresponding to the new sharp feature is unclear. However, its appearance could explain why the lifetime results do not meet the traditional model when we tested ultrathin dielectrics.

Study of Stress Migration Failure in SiLK™/SiO2 Hybrid Cu Interconnects

Stress migration (SM) behavior is studied for a 130nm‐node SiLK™/SiO2 hybrid structure in which the interlevel dielectrics (ILD) consist of SiLK™ for trench levels and SiO2 for via levels. The failure rate dependence on the temperature, line width and circuit is examined in detail. Furthermore, an effect of dielectric deposition process on the reliability of the hybrid interconnects is investigated. It has been found that SM behavior is essentially similar to that reported in Cu/SiO2 systems. It has also been clarified that SiO2 PVD conditions at via level had a large impact on the failure rate. Therefore, the control of ILD deposition conditions is found to be one of the key factors in suppressing the SM failure. In order to examine the effect of the PVD conditions, the residual stress in vias were measured by using X‐ray diffraction method. The results show that σx (the stress component parallel to the surface) in vias greatly depends on the PVD conditions. Then, the relationship between the PVD conditi...