Hiromi Niiyama

High-performance 0.10- mu m CMOS devices operating at room temperature

The authors have fabricated 0.10- mu m gate-length CMOS devices that operate with high speed at room temperature. Electron-beam lithography was used to define 0.10- mu m polysilicon gate patterns. Surface-channel type p- and n-channel MOSFETs were fabricated using an LDD structure combined with a self-aligned TiSi/sub 2/ process. Channel doping was optimized so as to suppress punchthrough as well as to realize high transconductance and low drain junction capacitance. The fabricated 0.10- mu m CMOS devices have exhibited high transconductance as well as a well-suppressed band-to-band tunneling current, although the short-channel effect occurred somewhat. The operation of a 0.10- mu m gate-length CMOS ring oscillator has been demonstrated. The operation speed was 27.7 ps/gate for 2.5 V at room temperature, which is the fastest CMOS switching ever reported.<<ETX>>

Inverter performance of 0.10 /spl mu/m CMOS operating at room temperature

The switching performance of 0.10 /spl mu/m CMOS devices operating at room temperature has been discussed on the basis of both experimental and simulated results. The measured propagation delay time of a 0.10 /spl mu/m gate length CMOS has been quantitatively divided into intrinsic and parasitic components for the first time. The results have shown that the drain junction capacitance strongly affects the propagation delay time in the present 0.10 /spl mu/m CMOS. The switching performance of a 0.10 /spl mu/m ground rule CMOS has been simulated by using device parameters extracted from the experimental results. In the 0.10 /spl mu/m ground rule CMOS, it has been shown that an increase of the contact resistance will degrade the propagation delay time, which is one of the most essential problems in further device miniaturization. It has been also demonstrated that even if the specific contact resistance /spl rho//sub c/ is reduced to be less than 1/spl times/10/sup -7/ /spl Omega/ cm, further reduction of the gate overlap capacitance C/sub ov/ will be required to achieve the propagation delay time to be less than 10 ps in the 0.10 /spl mu/m ground rule CMOS at room temperature. >

Silicon-Based Single-Electron-Tunneling Transistor Operated at 4.2 K

We have fabricated single-electron-tunneling transistors using silicon which is a useful material for device applications. The device is composed of thin polycrystalline silicon film patterned by electron-beam lithography and its thermally grown oxidized film. We have observed, in this device, periodic conductance oscillations as a function of gate voltage and nonlinear resistances as a function of drain voltage at 4.2 K. These experimental results are in agreement with the theory of Coulomb blockade. We conclude that the observed behavior results from the charging energy of single-electron tunneling.

Performance fluctuations of 0.10 /spl mu/m MOSFETs-limitation of 0.1 /spl mu/m ULSIs

The authors have recently demonstrated that 0.1 /spl mu/m gate length CMOS devices normally operate at room temperature. Moreover, they have experimentally shown that the threshold voltage of MOSFETs fluctuates due to the statistical fluctuations of channel dopant number, n/sub a/, which increases by reducing the gate length. Even if the individual 0.1 /spl mu/m MOSFETs operate normally, can one succeed in fabricating 0.1 /spl mu/m region ULSIs without failure ? To obtain the answer, it is necessary to study the performance fluctuations of 0.1 /spl mu/m region MOSFETs. This paper discusses the peculiar fluctuations of the threshold voltage and the transconductance of 0.10 /spl mu/m gate length NMOSFETs, using an 8 k MOSFET array and mentions their physical mechanism. Finally, the performance fluctuations of 0.1 /spl mu/m region ULSIs are estimated.<<ETX>>

A High-Performance 0.05 µm SOI MOS FET: Possibility of Velocity Overshoot

A high-transconductance 0.05 μm n-channel metal-oxide-semiconductor field-effect transistor (MOS FET) has been realized using thin silicon on insulator (SOI)/buried oxide structures. The measured and the intrinsic transconductance values are 472 mS/mm and 702 mS/mm, respectively. These are the highest G m values yet reported for SOI MOS FET. Electron velocity, however, is 82% of the bulk saturation velocity, u sat . This is mainly due to the degradation of the mobility caused by scattering in the SOI layer and the temperature increment induced by the self-heating effect. Therefore, it is important to achieve both mobility-degradation-free and self-heating-free conditions in order to realize a high-speed SOI MOS FET using the carrier velocity overshoot.

Improved Electron-Beam/Deep-Ultraviolet Intralevel Mix-and-Match Lithography with 100 nm Resolution

We have developed a novel electron-beam (e-beam)/deep-ultraviolet (DUV) intralevel mix-and-match (ILM&M) lithography as a production-viable technology. The main feature of the ILM&M lithography is its use of a DUV biased exposure method for increased throughput and a combination of a variably shaped e-beam/character projection writer with a step-and-repeat DUV scanning system for accurate intralevel butting between e-beam and DUV patterns. It was demonstrated that the throughput of e-beam writing in the ILM&M lithography could reach about three times that of e-beam lithography, and that an intralevel butting accuracy of less than 50 nm could be achieved. The proposed ILM&M has been successfully applied to the development and early production of leading edge devices at our laboratory.

Optimization of a high-performance chemically amplified positive resist for electron-beam lithography

We report on sub-0.1 μm electron-beam (EB) lithography using a new chemically amplified positive resist with a stabilizing additive. Diphenylamine (DPA) was incorporated into the resist formulation as a stabilizing additive. DPA improves the post-exposure delay (PED) stability. Even after a PED of 60 min in a clean-room atmosphere (NH 3 concentration ∼20ppb), no insoluble surface layer was observed for the resist with DPA. High sensitivity and resolution could be achieved by optimizing process conditions such as baking and developer. 0.1 μm lines-and-spaces (L/S) patterns and 0.08 μm hole patterns were obtained using a 50 kV variably shaped beam EB system. The practical sensitivity was 6 μC/cm 2 for L/S patterns. Our resist system also shows good performance as an etching mask. A 0.1 μm diameter hole which was 0.5 μm etched in silicon oxide using a 0.5 μm thick resist could be obtained in this experiment.

Reduction of surface roughness and defect density by cryogenic implantation of arsenic

A defect-free diffusion layer is found to be formed by the cryogenic ion implantation technique for arsenic dopants. The following thermal annealing completely recrystallizes amorphous layers through solid-phase growth, eliminating dislocation growth. Furthermore, substrate cooling drastically suppresses the melting of the substrate surface. It is considered that, owing to the ability to absorb thermal energy brought about by cooling the substrate, the number of local microvoids formed by vacancy clusters is reduced and interstitial clusters are not easily enlarged, leading to surface roughness reduction. The substrate-cooling technique is very effective for suppressing recrystallization bought about by the self-annealing effect, and it is a very effective technology not only for reducing the defect density but also for improving the Si/SiO2 interface state density.

Improvement of P?N Junction Leakage and Reduction in Interface State Density in Transistors by Cryo Implantation Technology

Cryo implantation by a rapid thermal annealing process was applied to achieve defect-free shallow junctions. Boron ions were implanted in (100) Si substrates cooled using liquid nitrogen, with temperature controlled at -160 °C or lower during ion implantation. It was found that an amorphous layer was formed by boron implantation and that the amorphous layer completely recovered to single crystals after annealing at 900 °C for 30 s. No dislocation was observed in the implanted layer. It was also found that the thermal diffusion of boron was suppressed by cryo implantation. Furthermore, cryo implantation was found to be very effective in reducing the density of defects, and P–N junction leakage was reduced by one order of magnitude compared with that in the case of room temperature implantation. These results suggest that the transient enhanced diffusion of boron can be reduced by suppressing vacancy migration toward the surface during implantation. Moreover, the substrate-cooling effect is very effective for improving surface roughness, and it is a very effective technology not only for reducing Si/SiO2 interface state density but also for improving the reliability of gate oxide.

Ultralow Contact Resistivity for a Metal/p-Type Silicon Interface by High-Concentration Germanium and Boron Doping Combined with Low-Temperature Annealing

A contact resistivity of 6.9×10-9 Ωcm2 has been obtained in an AlSi (1 wt %)–Cu (0.5 wt %) alloy/silicon system by using heavy-dose ion implantations of germanium and boron combined with low-temperature annealing. The analysis of the combined state showed that B12 cluster was incorporated and the supersaturation activation layer was formed into the region where germanium separated. Separated germanium is expected to have high interface state density. It is considered that this interface state density also has a Fermi level, and in order to reduce the difference from the Fermi level of the substrate, the charge moves to interface state density from the substrate. As a result, it is not based on a metallic material but a work function becomes small because pinning by which a Fermi level is fixed to interface state density occurs owing to the substrate/metal interface. It is considered to be attributable to the existence of a Ge-rich layer formed by low-temperature annealing, and a supersaturation activation layer that lowers contact resistance was formed.