Atsushi Murakoshi

10-15 nm ultrashallow junction formation by flash-lamp annealing

Flash-lamp annealing (FLA) technology, a new method of activating implanted impurities, is proposed. FLA is able to reduce the time of the heating cycle to within the millisecond range. With this technology, an abrupt profile is realized, with a dopant concentration that can exceed the maximum carrier concentration obtained by conventional rapid thermal annealing (RTA) or furnace annealing. In contrast to a laser annealing method, FLA can activate dopants in an 8-inch-diameter substrate and, simultaneously, strictly control diffusion of dopants so as not to melt the substrate surface by radiation. FLA presents the possibility of fabricating sub-0.1-µm MOSFETs with good characteristics.

Technology trends of silicon-on-insulator-its advantages and problems to be solved

Recent progress in SOI technology is reviewed and problems which need be solved are discussed. Emphasis is placed on the substrate floating effect, for which the bandgap engineering method is proposed for the first time. It is demonstrated that Si-Ge formation in the source region can improve the drain breakdown voltage significantly.<<ETX>>

Suppression of the floating-body effect in SOI MOSFET's by the bandgap engineering method using a Si/sub 1-x/Ge/sub x/ source structure

The bandgap engineering method using a SiGe source structure is presented as a means to suppress the floating-body effect in SOI MOSFETs. Experiments using Ge implantation are carried out to form a narrow-bandgapped SiGe layer in the source region. It has been confirmed that Ge-implanted SIMOX exhibited a 0.1 eV bandgap narrowing with a relatively low Ge-dosage of 10/sup 16/ cm/sup -2/. The fabricated N-type SOI-MOSFETs exhibited suppressed parasitic bipolar effects, such as improvement of the drain breakdown voltage or latch voltage, and suppression of abnormal subthreshold slope. Advantages over other conventional methods are also discussed, indicating that the bandgap engineering provides a practical method to suppress the floating-body effect.

Hole generation by icosahedral B12 in high‐dose boron as‐implanted silicon

It was found that a high concentration of holes was generated without any post‐annealing by boron ion implantation into silicon in the high‐dose region of more than 1×1016 cm−2. X‐ray photoelectron spectroscopy and Fourier transform infrared absorption spectrum revealed that B12 icosahedra were created just after implantation. The generation of holes can be explained by the model in which B12 icosahedra act as a double acceptor.

Hole Generation without Annealing in High Dose Boron Implanted Silicon: Heavy Doping by B12 Icosahedron as a Double Acceptor

A high hole concentration region of about 1×1021 cm-3 was generated without any post-annealing by the implantation of high doses of boron into silicon substrates. X-ray photoelectron spectroscopy (XPS) measurement and Fourier transform IR spectroscopy (FTIR) absorption spectra revealed that B12 icosahedra were created in as-implanted samples. A new model of the generation of holes is proposed in which B12 icosahedron acts as a double acceptor.

Accurate SIMS depth profiling for ultra-shallow implants using backside SIMS

We studied accurate depth profiling for ultra-shallow implants using backside SIMS. In the case of measuring ultra-shallow profiles, the effects of surface transient and knock-on are not negligible. Therefore, we applied backside SIMS to analyze ultra-shallow doping to exclude these effects. Comparing the SIMS profiles of surface-side and those of backside, backside profiles show a sharper ion implantation tail than surface-side profiles. Furthermore, backside SIMS profiles show almost no dependence on primary ion energy. This indicates that backside SIMS provides sharp B profiles suitable for analyzing ultra-shallow implants, using higher primary ion energy in comparison with implantation energy. The backside SIMS technique has a good potential to be used for next generation devices.

Flash Lamp Anneal Technology for Effectively Activating Ion Implanted Si

Device miniaturization requires reduction of the thermal budget in the annealing process for ultra-shallow junction and ultra-thin gate oxide. Recently, spike anneal technology has considerably reduced the time of the heating cycle. In heating the substrate above 1000°C, however, the total time of ramp-up and rampdown takes 10 sec or above. In order to minimize the heating cycle, we newly developed a flash lamp anneal (FLA) technology. FLA was able to reduce the heating cycle within the millisecond range and was successfully applied to activation process by combining appropriate assist heating. In this paper, we first report fundamental results on electrical activation of impurities by using FLA technology.

Advanced Ion Implantation Technology for High Performance Transistors

Cryo-implantation technology is proposed for reducing crystal defects in Si substrates. The substrate temperature was controlled to be below at -160°C during ion implantation. No dislocation was observed in the implanted layer after rapid thermal annealing. Pn junction leakage was successfully reduced by one order of magnitude as compared with room temperature implantation. Precise dose control is indispensable in channel region of high performance MOSFETs. In order to improve the precision of implanted dose, chip size implantation technology without photoresist mask was developed. In this technology, chip-by-chip implantation can be carried out by step-and-repeat wafer stage, and different implantation conditions are available in the same wafer independent of wafer size.

Ru Electrode Deposited by Sputtering in Ar/O2 Mixture Ambient.

Ru films are fabricated by dc magnetron sputtering in an Ar/O2 ambient, as the bottom electrodes of Ba0.5Sr0.5TiO3 thin film capacitors. The Ru films deposited on Si in an Ar/O2 mixture ambient show low resistivity and low film stress and do not form Ru2Si3 following thermal processing even at 700°C. It becomes clear that there exist very thin amorphous and crystalline layers composed of Ru, Si and O between the Ru films and Si in the case of Ru films deposited in an Ar/O2 ambient. A low contact resistance at the Ru/n+-Si interface is obtained after annealing at 700°C. An effective SiO2 film thickness of 0.42 nm is obtained for an actual Ba0.5Sr0.5TiO3 film thickness of 42 nm with a leakage current of less than 1×10-8 A/cm2 in the range between -1.5 V and +1.8 V for a Ru/Ba0.5Sr0.5TiO3/Ru/n+-Si capacitor without a barrier metal layer.

Increase of parasitic resistance in shallow p/sup +/ extension by SiN sidewall process and its improvement by Ge preamorphization for sub-0.25-/spl mu/m pMOSFET's

Anomalously high parasitic resistance is observed when SiN gate sidewall spacer is incorporated into sub-0.25-/spl mu/m pMOSFETs. The parasitic resistance in p/sup +/ S/D extension region increases remarkably by decreasing BF/sub 2/ ion implantation energy to lower than 10 keV. It is confirmed that low activation efficiency of boron in p/sup +/ extension is the reason for such high parasitic resistance. The reduction of activation efficiency of boron may result from hydrogen passivation of boron acceptor; Fourier transform infrared absorption (FT-IR) measurement suggests that diffused hydrogen from SIN into p/sup +/ extension region forms the silicon-hydrogen-boron complex. It is also found that the activation efficiency of boron correlates well both with implantation energy of BF/sub 2/ and the amorphization rate of substrate. Therefore, in sub-0.25-/spl mu/m era, the extra amorphization step is essential not only to form a shallow junction but also to enhance boron activation. Germanium preamorphization implantation (Ge PAI) is hence applied to p/sup +/ extension of 0.15 /spl mu/m pMOSFETs. It is finally demonstrated that this Ge PAI process reduces the total parasitic resistance to improve the drain saturation current by up to 10%.