Shuji Sone

A stacked capacitor technology with ECR plasma MOCVD (Ba,Sr)TiO/sub 3/ and RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes for Gb-scale DRAMs

A Gb-scale DRAM stacked capacitor technology with (Ba,Sr)TiO/sub 3/ thin films is described, The four-layer RuO/sub 2//Ru/TiN/TiSi/sub x/, storage node configuration allows 500/spl deg/C processing and fine-patterning down to the 0.20 /spl mu/m size by electron beam lithography and reactive ion etching. Good insulating (Ba/sub 0.4/Sr/sub 0.6/)TiO/sub 3/ (BST) films with an SiO/sub 2/ equivalent thickness of 0.65 nm on the electrode sidewalls and leakage current of 1/spl times/10/sup -/6 A/cm/sup 2/ at 1 V are obtained by ECR plasma MOCVD without any post-deposition annealing, A lateral step coverage of 50% for BST is observed on the 0.2 /spl mu/m size storage node pattern, and the BST thickness on the sidewalls is very uniform, thanks to the ECR downflow plasma. Using this stacked capacitor technology, a sufficient cell capacitance of 25 fF for 1 Gb DRAMs can be achieved in a capacitor area of 0.125 /spl mu/m/sup 2/ with only the 0.3 /spl mu/m high-storage electrodes.

An ECR MOCVD (Ba,Sr)TiO/sub 3/ based stacked capacitor technology with RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes for Gbit-scale DRAMs

A high dielectric constant (Ba,Sr)TiO/sub 3/ [BST] based stacked capacitor with new RuO/sub 2//Ru/TiN/TiSi/sub x/ storage nodes was developed for Gbit-scale DRAMs. Good insulating BST films with a small t/sub eq/ of 0.65 nm on the electrode sidewalls were obtained by ECR MOCVD. The four-layer storage node allows 500/spl deg/C processing and fine-patterning down to 0.20 /spl mu/m by EB lithography and RIE. A cell capacitance of 25 fF in 0.125 /spl mu/m/sup 2/ is achieved using 0.3 /spl mu/m-high storage electrodes for 1 Gbit DRAMs.

Low temperature deposition of (Ba, Sr)TiO3 films by electron cyclotron resonance plasma chemical vapor deposition

(Ba, Sr)TiO 3 films deposited by electron cyclotron resonance plasma chemical vapor deposition at 450°C and 500°C are investigated. The crystallinity, evaluated by X-ray diffraction and by measuring grain size, and electrical properties of films were evaluated for changes in deposition temperature, deposition rate, and Ba content, without a post-deposition annealing. Slower deposition rates as well as higher deposition temperatures were found to improve film crystallinity. Evaluation of electrical properties and film crystallinity revealed that the optimum Ba content of a film deposited at 500°C was 0.4. A 27nm thick film deposited on a Pt substrate at 500°C and at 1.1 nm/min with a Ba content of 0.4 exhibited a SiO 2 equivalent thickness of 0.65 nm and a leakage current density of 4.6 x 10 -7 A/cm 2 at 1V. The film composition was found to be sufficiently uniform throughout, i.e., from the top to the side of the films on a stacked bottom electrode.

A stacked capacitor with an MOCVD-(Ba,Sr)TiO/sub 3/ film and a RuO/sub 2//Ru storage node on a TiN-capped plug for 4 Gbit DRAMs and beyond

A stacked high-/spl epsiv//sub r/ capacitor is fabricated using a 550/spl deg/C-process-tolerant RuO/sub 2//Ru storage node on a TiN-capped plug and an ECR plasma MOCVD (Ba,Sr)TiO/sub 3/ (BST) thin film with small SiO/sub 2/ equivalent thickness (t/sub eq/) of 0.40 nm. The contact resistance (Rc) of a 0.15 /spl mu/m diameter (/spl phi/) contact is as low as 50 k/spl Omega/. With this capacitor technology, a cell capacitance (Cs) of 25 fF is achieved in projected areas of 0.055 /spl mu/m/sup 2/ for 4 Gbit DRAMs and 0.031 /spl mu/m/sup 2/ for 16 Gbit DRAMs with 0.25 /spl mu/m- and 0.37 /spl mu/m-high storage nodes.

An Analysis on the Driving Force and Optimum Frequency of a Noncontact-Type Ultrasonic Motor

A Noncontact-type ultrasonic motor driven by the radiation pressure of the sound waves can be rotated well and miniaturized. In the previous study, the maximum revolution speed reached 4,000 rpm in the case of a small ultrasonic motor of 5 mm diameter and 0.5 mm thickness. In this paper, a consideration of the driving force of such a noncontact ultrasonic motor is described.

Electrical Properties of (Ba, Sr)TiO3 Films on Ru Bottom Electrodes Prepared by Electron Cyclotron Resonance Plasma Chemical Vapor Deposition at Extremely Low Temperature and Rapid Thermal Annealing

(Ba, Sr)TiO3 (BST) films were prepared on Ru bottom electrodes by electron cyclotron resonance chemical vapor deposition at extremely low temperature and rapid thermal annealing (RTA). Leakage current characteristics were improved by lowering the BST deposition temperature down to 120°C. (Ba+Sr)-rich films with a (Ba+Sr)/Ti ratio of 1.1–1.5 had lower leakage current densities than stoichiometric and Ti-rich films with a ratio of 0.8–0.9. Cross sectional transmission electron microscopy observations showed that the 120°C-deposited and 700°C-RTA-treated (Ba+Sr)-rich film had a granular structure and smooth interfaces with the electrodes. The stoichiometric and Ti-rich films had columnar structures and larger interface roughness. As a result, low leakage current density less than 10-7 A/cm2 at ±1 V were obtained for 30 nm-thick BST films with a (Ba+Sr)/Ti ratio of 1.1–1.5 by combination of 120°C deposition and 700°C RTA.

Plasma CVD of (BaSr)TiO3 Dielectrics for Gigabit DRAM Capacitors

Electron cyclotron resonance (ECR) plasma chemical vapor deposition (CVD) of (BaSr)TiO3 dielectrics is reviewed. The oxygen plasma lowered the crystallization temperature and carbon contamination. (BaSr)TiO3 CVD process was developed under conditions of relatively low deposition rate of 1.1 nm/min and a relatively low deposition temperature of 550°C. Utilizing this process, we developed a gigabit dynamic random access memory (DRAM) capacitor technology involving the preparation of a thin (BaSr)TiO3 capacitor dielectric over a RuO2/Ru storage node contacting a TiN/TiSiX/poly-Si plug. The ECR plasma CVD enabled uniform deposition of gigabit-DRAM-quality (BaSr)TiO3 films on the electrode sidewalls. The storage node contact improved in endurance against oxidation, by fabricating the buried-in TiN/TiSiX plug (TiN-capped plug) under the RuO2/Ru storage node. (BaSr)TiO3 films with a small equivalent SiO2 thickness of 0.38 nm and a leakage current density of 8.5×10−7 A/cm2 at an applied voltage of 1.0 V, were obtained without any further annealing process. An equivalent SiO2 thickness of 0.40 nm on the RuO2 sidewall was also achieved. It is concluded that this technology has reached the requirements for gigabit DRAM capacitors.

Low Temperature Recovery of Ru/(Ba, Sr)TiO3/Ru Capacitors Degraded by Forming Gas Annealing

A low temperature N2 post-annealing process was proposed to improve the degradation of Ru/(Ba, Sr)TiO3/Ru capacitors due to forming gas annealing. After N2 post-annealing at 300°C, the leakage current degraded by forming gas annealing was completely recovered to the initial level without affecting the SiO2 equivalent thickness of 0.51 nm. No degradation of the subthreshold characteristics of n-channel metal-oxide-semiconductor field effect transistors and N+P junction leakage current by the post-annealing was also confirmed. The Ru/(Ba, Sr)TiO3/Ru capacitor technology with this post-annealing process is suitable for dynamic random access memories in 0.13 µm generation and beyond.