Hiroshi Koizumi

A 12.5Gb/s CMOS BER test using a jitter-tolerant parallel CDR

Implemented in a 0.13 /spl mu/m CMOS process, pulse pattern generation and BER test functions are integrated in a chip. A parallel CDR (clock data recovery) circuit provides 12.5 Gb/s operation and wide tolerance of over 0.5 UIpp for 4 to 80 MHz sinusoidal jitter.

10.3-Gb/s burst-mode CDR with idle insertion and digital calibration in 40-nm CMOS for 10G-EPON systems

A burst-mode CDR (B-CDR) suffers from a trade-off between jitter transfer and lock time. To solve the trade-off, we utilize a continuous-mode CDR (C-CDR) after a B-CDR with converting the burst signal to the quasi-continuous signal by idle insertion. The B-CDR, designed in 40-nm CMOS, also employs a fully digital, 6-bit automatic frequency calibrator for compensating the process variation. It calibrates the oscillation frequency of the VCO in the B-CDR from 10.3 GHz ± 2 GHz to 10.3 GHz ± 60 MHz. The B-CDR, integrated with the C-CDR, achieves output-data-jitter reduction of 17.3 dB at jitter frequency of 300 MHz and lock time of 220 ns, complying with the 10G-EPON standard.

20.1-mW 8-Gbps UWB-IR millimeter-wave transmitter using an OOK pulse modulator based on CMOS inverters

We propose a low-power millimeter-wave ultra-wideband impulse radio (UWB-IR) transmitter using an on/off keying (OOK) pulse modulator for wireless connection or dielectric-waveguide interconnects. To achieve low-power consumption, we use a low-power OOK pulse modulator consisting of only four CMOS inverters and passive elements. The proposed transmitter was fabricated in 65-nm CMOS technology. It exhibits the maximum data rate of 8 Gbps, output power of -15.6 dBm, power consumption of 20.1 mW, and power efficiency of 2.5 mW/Gbps at an operating frequency of 50 GHz.

Analysis and design based on small-signal equivalent circuit for a lO-GHz ring VCO with 65-nm CMOS

An analysis and design method for a 10-GHz ring voltage-controlled oscillator (VCO) are proposed. By using a detailed small-signal equivalent circuit model, the delay of the current mode logic buffer circuit and the minimum limit of the number of those used in the VCO are evaluated. We set the transconductance generator in a MOSFET model as a function of drain current and obtained the current dependence of the oscillation frequency of the VCO. To confirm the validity of the design method, we compared the measured and estimated oscillation frequency of the VCO fabricated with the 65-nm MOSFET process. The agreement between the measurements and calculations is good enough, confirming the validity of the method.

A 10Gb/s burst-mode laser diode driver for burst-by-burst power saving

A burst-mode laser diode driver circuit (BLDD) for 10Gb/s-class passive optical network (10G-EPON) systems reduces power consumption by 94% while the laser diode (LD) is in the off state. The off-state optical launch power is kept at less than -45dBm while meeting the transistor breakdown condition. The BLDD recovers to the active state within 16ns, which is 46x faster than that of a previously reported burst-mode transmitter, and the fast recovery makes efficient burst-by-burst power saving possible.

A PVT Tolerant STM-16 Clock-and-Data Recovery LSI Using an On-Chip Loop-Gain Variation Compensation Architecture in 0.20-μm CMOS/SOI

This paper proposes an on-chip loop gain variation compensation architecture for a clock and data recovery (CDR) LSI. The CDR LSI using the proposed architecture can meet the jitter specifications recommended in ITU-T G. 958 under wide variation of temperature and supply voltage. The relation between the jitter specifications and the loop gain is derived theoretically. Gain-variation characteristics of component circuits are studied by circuit simulation. The proposed architecture uses voltage controllers to reduce the gain variation of the LC voltage controlled oscillator (LC-VCO) circuit and charge-pump circuit. The voltage controllers are designed to have a first-order positive coefficient to temperature, which is found by an analysis of the gain variation characteristics. An STM-16 CDR with the proposed architecture is implemented in 0.20-μm fully depleted CMOS/SOI. The CDR shows a wide capture range of ±140MHz and meets both the jitter transfer and the jitter tolerance specifications in the ambient temperature range from -40 to 85°C and with the supply voltage variation of ±6%.