Hiroshi Makihira

Automated visual inspection for lsi water multilayer patterns by cascade pattern matching algorithm

This paper reports on the defect detection algorithm for the LSI wafer multilayer patterns, together with the result of evaluation. The multilayer patterns are constructed by the exposure after alignment between the wafer pattern and the reticle pattern for each chip. Consequently, the position relation between layers is different even for adjacent chips (interlayer registration error). The developed algorithm compares the gray-level images of adjacent chips on the wafer and extracts the defect without being affected by the inter-layer registration error. First, the pattern edge is extracted from the gray-level image, and the position alignment is executed using the edges. Then, by eliminating the region where gray levels are equal, the regions are extracted for which the position alignment is unsatisfactory. The position alignment is attempted again for that region. This procedure is iterated. When the unmatched region of the pattern edge is sufficiently small, it is decided that the interlayer registration error is absorbed, and the unmatched region is extracted as the defect. An automatic visual inspection system was constructed and evaluated experimentally. As a result, it was verified that the whole chip area can be inspected, and the defect of 0.5 μm or more can be detected in a stable way.

Automated visual inspection for LSI wafer patterns using a derivative-polarity comparison algorithm

Algorithms for visual inspection of LSI wafer multilayer patterns have been developed. These algorithms compare corresponding images of two dies on a wafer. In this paper, two algorithms are proposed. The derivative-polarity comparison algorithm compares the polarities of the first derivatives of two images, and recognizes the regions whose polarities are not matched as positional discrepancies (defects), in order to cope with gray-scale differences caused by pattern thickness errors. The multiple-displacement pattern matching algorithm executes the above polarity comparisons at several positions with images suitably aligned, and determines the common unmatched regions as defective, in order to handle the interlayer- registration errors encountered with multilayer patterns. These algorithms were evaluated experimentally, and it was verified that defects of 0.3 micrometers or more can be reliably detected in multilayer patterns by combining these algorithms.

Study on Automatic Visual Inspection of Shadow-Mask Master Patterns

Abstract An automatic appearance inspection technique for C.P.T. shadow-mask master patterns has been developed. The system structure of the automatic inspection machine, characteristics on the pattern detection, algorithm of judgment and the experimental results are reported.

Pattern Inspection Techniques for SEM Image

We have developed pattern inspection techniques for Integrated Circuit elements which use an SEMI (Scanning Electron Microscope). In this paper we will discuss the transformation of low SP1 ratio SEM image signals into binary values, detection techniques using the SEM to detect patterns on insulating materials, and detection algorithms for defects.

Optimum threshold generation for automated visual inspection of large‐scale integration wafer patterns

The authors have developed a submicron-level defect detection method that avoids the unnecessary detection of grains produced by some layers. As part of an automated visual inspection system for Large-Scale Integration wafer multilayer patterns, the developed method can detect defects reliably by automatically generating an optimum threshold for each pattern according to the occurrence of grains in each area of the pattern, and then binarizing the subtracted grayscale images with the threshold. This method is used in comparison inspections of periodic cell patterns in the same die. This can be realized without using design pattern and process information. This paper proposes an edge-preserving grain-noise smoothing algorithm that generates a uniform threshold for each region surrounded by the pattern edges according to the grains detected using the multiple cell patterns to be inspected. It is confirmed through experiments with actual LSI wafers that defects on the order of 0.5 μm and greater, which exist at pattern edges and in the regions having no grains, can be detected stably without the unnecessary detection of grains, even with grain sizes on the order of 1 ∼ 1.3 μm in some layers.

Threshold setting assisted by numerical analysis methods in automatic visual inspection using gray‐scale image comparison

A method is proposed to support fast product-specific threshold setting in case of inspection by comparison of gray-scale images. With the proposed method, emphasis is laid on false alarms (false recognition of normal parts as defects), and the optimal threshold is set as the minimum value to keep the false alarm rate within acceptable limits. The proposed procedure of threshold setting consists of three stages, namely, calculation of initial threshold, preliminary inspection/review, and threshold correction. In initial threshold calculation and threshold correction, fast threshold renewal is obtained by numerical analysis, specifically, by successive approximations. The proposed method was applied to an actual device for visual inspection of LSI wafer patterns and proved to offer fast and efficient threshold setting. Thus, the threshold now can be set efficiently for specific products in an LSI production line, ensuring adequate feedback at a low false alarm rate. This implies flexible inspection in multi-item production with prompt adjustment to new products.

STUDY ON AUTOMATIC VISUAL INSPECTION OF SHADOW-MASK MASTER PATTERNS

An automatic appearance inspection technique for C.P.T. shadow-mask master patterns has been developed. The system structure of the automatic inspection machine, characteristics on the pattern detection, algorithm of judgment and the experimental results are reported.