Masakazu Hioki

Performance and yield enhancement of FPGAs with within-die variation using multiple configurations

A new method for improving the timing yield of field-programmable gate array (FPGA) devices affected by random within-die variation is proposed. By selection of an appropriate configuration from a set of functionally equivalent configurations such that the critical paths do not share same circuit resources on the FPGA, both the average critical path delay and its standard deviation are reduced substantially under conditions of large random variation. Large within-die variations of device parameters such as transistor threshold voltage are anticipated in future semiconductor technologies, resulting in degradation of parametric yields. Comparing to the previous approach which compensates for such within-die variation by designing circuit placement for each chip using variation information measured before, our method does not require the measurement of process variations and execution of design tools for each chip. The average critical path delay is reduced by up to 5% assuming 30% (σ/μ) variation in threshold voltage, with a corresponding 50% decrease in standard deviation.

Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations

A new method for improving the timing yield offield-programmable gate array (FPGA) devices affected by intrinsicwithin-die variation is proposed. The timing variation is reducedby selecting an appropriate configuration for each chip from a setof independent configurations, the critical paths of which do notshare the same circuit resources on the FPGA. In this article, theactual method used to generate independent multiple configurationsby simply repeating the routing phase is shown, along with theresults of Monte Carlo simulation with 10,000 samples. Onesimulation result showed that the standard deviations of maximumcritical path delays are reduced by 28% and 49% for 10% and 30%Vth variations (σ/ μ), respectively,with 10 independent configurations. Therefore, the proposed methodis especially effective for larger Vth variation and isexpected to be useful for suppressing the performance variation ofFPGAs due to the future increase of parameter variation. Anothersimulation result showed that the effectiveness of the proposedtechnique was saturated at the use of 10 or more configurationsbecause of the degradation of the quality of the configurations.Therefore, the use of 10 or fewer configurations is reasonable.

Fully-functional FPGA prototype with fine-grain programmable body biasing

A fully-functional FPGA prototype chip in which the programmable body bias voltage can be individually applied to elemental circuits such as MUXes, LUT and DFF is fabricated using low-power 90-nm bulk CMOS technology and the area overhead, dynamic current, static current and operational speed are evaluated in silicon. In measurements, 10 ISCAS benchmark circuits are implemented by employing newly developed CAD tools which consist of VT mapper as well as placer and router. Mask layout shows that well-separated margins, programmable body bias circuits, and additional configuration memories occupy 54% of the FPGA tile area. Measurement results show that the fabricated FPGA reduces the static current by 91.4% in average. In addition, evaluations by implementing ring oscillator with various body bias voltage pairs demonstrate the static current reduction from 23.1 uA to 1.0 uA by assigning low threshold voltage and high threshold voltage to MOSFETs on a critical path and the rest of the MOSFETs, respectively while maintaining the same oscillation frequency of 6.6 MHz as the frequency when all MOSFETs are assigned low threshold voltage. Moreover the fine-grain programmable body bias technique accelerates the oscillation frequency of ring oscillator implemented on FPGA by aggressively applying forward body bias voltage, while assignment of HVT to MOSFETs on the non-critical path by applying the reverse body biasing effectively suppresses exponential increase of static current caused by the forward body biasing.

Optimal set of body bias voltages for an FPGA with field-programmable V/sub th/ components

An FPGA with field-programmable Vth components can attain both high performance and low power consumption, without placement and routing constraints, by flexibly controlling the threshold voltage (Vth) of transistors. Since Vth for transistors for a specific circuit block in an FPGA is chosen from a set of Vth values defined by body bias voltage set (BBVS), adequate selection of BBVS is important in the design decision process in a field-programmable Vth method. In this paper, the effect of the selection of BBVS on static power reduction in an FPGA with field-programmable Vth components was presented. To select the optimal BBVS among several supplied body bias voltage candidates, several BBVSs are provided. The results show that the best BBVS achieves remarkable static power reduction, to as little as 1/30 the value in a conventional FPGA without performance degradation. In addition, the study on the optimal selection of body bias voltage for high-Vth transistor in a BBVS reveals that deep reverse body bias for high-Vth transistor does not necessarily offer the optimal condition, and optimization is necessary

Utility of high on-off ratio, high off resistance rewritable device to EEPROM for ultra-low voltage operation of steep subthreshold slope FETs

This paper proposes the utility of the solid-electrode nanometer switch device called atom switch for ultra-low voltage EEPROM of near- or sub-60mV/dec. steep subthreshold slope transistors. We adopt combination of a simple inverter-sensing read circuit and the atom switch device. This circuit does not include sense amplifiers and not limited by operation limit of analog circuits. High on-off ratio and off resistance enable low-voltage operation with a simple inverter-sensing structure. We fabricated a TEG wafer in a 65nm process, and obtained measurement results of circuit operation in 350mV including the level shifter of memory cell selector driver and in 150mV with the read circuit only.

Evaluation of granularity on threshold voltage control in flex power FPGA

The flex power FPGA can flexibly control speed and power in a trade-off relationship by a flexible assignment of proper threshold voltage generated from body-bias units to transistors. This paper evaluates static power consumption and an area-overhead by the body-bias units on various threshold voltage control granularity in the flex power FPGA. There is also a trade-off relationship between the static power consumption and the area-overhead for granular control of the threshold voltages. Both a grain size and its style of division have a strong influence on the trade-off. Own evaluation results show that static power reduces less than 1/5 of original level, while increase an area overhead of less than 40%. If an area increase of 50% is allowed, then the reduction in static power consumption to 1/10 or less is obtained

More than an order of magnitude energy improvement of FPGA by combining 0.4V operation and Multi-Vt optimization of 20k body bias domains

In this paper, more than an order of magnitude (1/13) energy improvement of FPGA by combining low voltage operation and fine-grained body bias optimization is demonstrated from the measurement of the new SOTB implementation of Flex Power FPGA test chip.

Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA

This paper describes a new design concept, the Body Bias Voltage Set (BBVS), and presents the effect of the BBVS on static power, operating speed, and area overhead in an FPGA with field-programmable Vth components. A Flex Power FPGA is an FPGA architecture to solve the static power problem by the fine grain field-programmable Vth control method. Since the Vth of transistors for specific circuit blocks in the Flex Power FPGA is chosen from a set of Vth values defined by a BBVS, selection of a particular BBVS is an important design decision. A particular BBVS is chosen by selecting body biases from among several supplied body bias candidates. To select the optimal BBVS, we provide 136 BBVSs and perform a thorough search. In a BBVS of less Vth steps, the deepest reverse body bias for high-Vth transistors does not necessarily result in optimal conditions. A BBVS of 0.0 V and -0.8 V, which requires 1.65 times the original area, utilizes as little as 1/30 of the static power of a conventional FPGA without performance degradation. Use of an aggressive forward body bias voltage such as +0.6 V for lowest-Vth, performance is increased by up to 10%. Another BBVS of +0.6 V, 0.0 V, and -0.8 V reduces static power to 14.06% while maintaining a 10% performance increase, but it requires 2.75-fold area.

Preliminary performance analysis of flex power FPGA, a power reconfigurable device with fine granularity

The Flex Power FPGA design is presented as a novel FPGA design offering the ability to configure the trade-off between power consumption and speed for each logic element by adjusting the threshold voltage. This design targets the reduction of static power consumption, which has become one of the most important issues in the development of future-generation devices. A method to effectively assign threshold voltages to transistors at a prescribed granularity based on a timing analysis of the mapped circuit is implemented using the VPR simulator, and the static power reduction for 70 nm technologies is estimated using MCNC benchmark circuits. Simulation results show that the average static power can be reduced to as little as 1/30 of that in the corresponding conventional FPGA. This design is also demonstrated to be effective with future technologies, where the proportion of static power will be greater.

Reduction of overhead in adaptive body bias technology due to triple-well structure based on measurement and simulation

This paper presents the significant reduction of the area overhead due to triple-well structure for adaptive body bias methods. Triple-well TEGs which include violation of design rules originating from voltage tolerance were implemented on a 65nm process. Reexamining voltage tolerance based on measurement results reduced deep n-wells spacing by 60% on the 65nm process. A new method for further overhead reduction is proposed based on a device simulation which is validated with measurement results.