Hirotaka Nishino

Damage‐free selective etching of Si native oxides using NH3/NF3 and SF6/H2O down‐flow etching

Damage‐free selective etching of Si native oxides against Si has been achieved by NH3/NF3 and SF6/H2O down‐flow etching. In the NH3/NF3 etching, the wafer was covered with a film, and after its removal by heating above 100 °C, only SiO2 was found to be etched with an extremely high selectivity with respect to Si. Selective etching of Si oxides has also been obtained for SF6/H2O microwave discharge. In this case, a film of liquid solution containing HF and H2SOx is considered to form on the wafer surface. The selective etching of SiO2 takes place by the dissolved HF just as in the wet etching by an HF solution. The mechanisms of these selective reactions are discussed in detail based on the covalency of Si and SiO2 bondings.

High-performance FPGA based on novel DSS-MOSFET and non-volatile configuration memory (abstract only)

New FPGA deign using Dopant-Segregated Schottky MOSFET (DSS-MOSFET) and nonvolatile configuration memory (NCM) has been presented. Both of these devices can be fabricated by mature process for mass production. DSS-MOSFET has very low On-state resistance due to the high density dopant at source/drain junction. Therefore, FPGA is one of the best applications for the use of DSS-MOSFET since DSS-MOSFET can effectively improve not only CMOS logic performance but also pass-transistor logic performance. In addition, NCM with large On/Off resistance ratio, such as ionic memory, is adopted to replace SRAM-based configuration memory. Since NCM is fabricated between interconnect layers of CMOS, silicon area is smaller than in the case of SRAM. Furthermore, since NCM is a nonvolatile device, it is possible to reduce the power consumption by cutting off the power supply of unused circuit blocks. We developed a SPICE model of DSS-MOSFET to measure the delay of basic circuit in FPGA, and confirmed about 18% delay improvement for look-up-table with four to six inputs. We also designed physical layout to evaluate the area reduction of configuration memory, and verified the area of NCM is about 2.8X smaller than that of SRAM-based. Twenty largest MCNC benchmarks indicate that 26% improvement in critical path delay on average, and 15% improvement in area delay products on average can be achieved by the use of DSS-MOSFET and NCM.