Atsuko Sakata

Low-Temperature Graphene Growth Originating at Crystalline Facets of Catalytic Metal

We explored the characteristic behavior of low-temperature graphene growth on catalytic metal films. The results suggested that graphene growth originates from the crystalline facets with specific angles with respect to the crystalline orientation of the catalytic metals at low temperatures, which is different from the conventional growth models. The G/D ratio of the Raman spectrum of the graphene film was affected by both the number of specific facets and the width of the terrace. Because of this behavior, it is important to prepare the surface conditions with a smaller number of facets and a wider terrace for high-quality graphene growth at low temperatures.

Fabrication and Characterization of Planarized Carbon Nanotube Via Interconnects

We fabricate planarized carbon nanotube (CNT) via interconnects using chemical mechanical polishing (CMP). The selective growth of CNT bundles in via holes and the filling of spin-on-glass into the space among the CNTs are performed, followed by a CMP process. The via resistance is reduced by post-CMP treatment and post-annealing due to the improvement in the top contact formation. The measured CNT via resistance is higher than the CNT bundle resistance estimated from the measured resistance of an individual CNT. This indicates that contact resistance is higher than the CNT resistance in the CNT via interconnect.

Reliability Improvement by Adopting Ti-barrier Metal B for Porous Low-k IL Structure

This paper elucidated for the first time that titanium (Ti) is an excellent barrier metal (BM) material from the stand point of cost and performance, especially for the porous low-k ILD materials. Both stress induced voiding (SIV) suppression and one order longer electromigration (EM) lifetime were obtained by introducing Ti instead of the conventional tantalum (Ta). It has been considered that the smaller volume change when oxidized and the existence of metallic Ti-O solid-solution phase for Ti would be the reason for its control of moisture penetration from the low-k ILD materials which resulted in excellent SIV suppression. No electrical resistance increase due to intermetallic reaction between Cu and Ti was observed. Furthermore, the suppression of Cu grain boundary migration was attributed to the segregation of Ti atoms at the Cu grain boundaries. This resulted in higher interconnect reliability

BEOL process integration technology for 45 nm node porous low-k/copper interconnects

Highly reliable BEOL integration technology with porous low-k (k=2.3) was realized by development focusing on plasma damage control and moisture control. A hybrid dielectric scheme with damage resistant porous low-k films and buffer film was applied in view of its inherent advantages for realizing reliable porous low-k integration. A metallization process was developed from the viewpoint of suppressing morphology and adhesion degradation of barrier metal by oxidation. A dummy wiring pattern was also adopted to remove moisture absorbed in porous low-k films. Stress-migration and electromigration satisfying practical reliability were obtained with via size of 75 nm for the first time by utilizing all possible measures for reducing the damage and the moisture.

Highly reliable PVD/ALD/PVD stacked barrier metal structure for 45-nm node copper dual-damascene interconnects

In this paper, we describe highly reliable barrier metal structure for 45nm-node (140nm pitch) high performance copper interconnects. Issues and solutions for utilizing TaN barrier metal by atomic-layer deposition (ALD) process, which is the key technology for scaling down the barrier metal thickness, on low-k ILD materials were investigated. PVD/ALD/PVD stacked barrier metal structure was proposed from the viewpoint of factors affecting reliability such as stress-induced voiding (SiV) and electromigration (EM) endurance, and realized lower wiring resistance than that is attainable with the conventional process. We distinguished the role of each PVD film, and suggest the optimal barrier metal structure to realize highly reliable Cu dual-damascene interconnects.

Low resistive and highly reliable copper interconnects in combination of silicide-cap with Ti-barrier for 32 nm-node and beyond

Silicide-cap for Cu interconnects is promising for enhancing electromigration (EM) performance for 32 nm-node and beyond. But the trade-off properties of silicide-cap between line resistance and EM lifetime remain to be resolved. Increasing of line resistance is caused by Si diffusion in Cu line. So, we focused on Ti barrier metal (BM), which diffuses in Cu line, and applied it in combination with silicide-cap, in order to keep Si stable at the surface of Cu line. As a result, we achieved EM median time-to-failure (MTF) 100 times longer than that of the sample w/o silicide-cap and Ta-BM while line resistance is kept lower. Activation energy (Ea of EM of 1.45 eV is achieved.

Cu dual damascene process for 0.13 um technology generation using self ion sputtering (SIS) with ion reflector

Newly developed self ion sputtering(SIS) system is applied to Cu seed formation for electroplating (EP)-Cu filling. SIS is a bias sputtering using Cu/sup +/ ions generated by self sustained Cu plasma with controlling ion flux to a substrate by an ion reflector. This method can be realized by small modification of long throw sputtering (LTS) configuration. Substrate bias promotes transportation of Cu ions to the bottom of via holes efficiently from Cu plasma, which leads to improve step coverage. However, in the case of only applying substrate bias, uniformity of step coverage across the wafer can not be achieved to the objective value. Ion reflector converges ions on the wafer, especially on the edge of the wafer, then it improves uniformity of step coverage across the wafer. EP-Cu filling of vias of 0.2 um, A/R of 4 can be obtained using this method. Moreover, vias of 0.17 um, A/R of 5 can be completely filled when SIS is applied to barrier metal (TaN) deposition due to drastic improvement of TaN coverage.

Impact of oxygen on Cu surface for highly reliable low-k/Cu interconnects with CuSiN and Ti-based barrier metal

A trade-off property of CuSiN between EM improvement and line resistance increase was resolved by a breakthrough that leaves oxygen at grain boundary of Cu line surface before CuSiN formation. Then, the combination of CuSiN and Ti-rich TiN (Ti(N)) barrier metal (-BM) was applied. Oxygen left by weakening process strength of CuOx reduction lowered line resistance, because Si diffusion causing line resistance increase was controlled by the oxygen at grain boundary. Low-damage process of CuOx reduction also improved voltage ramp dielectric breakdown (VRDB) property. Excellent EM performance brought about by CuSiN was kept by the combination with Ti(N)-BM, because the oxygen made Si and Ti distributions uniform at grain boundary of Cu surface by forming Ti-silicide. Cu atom transport that caused EM failure was suppressed throughout grain boundary of Cu surface.

Graphene interconenets selectively grown on catalytic metal damascene structure and its growth mechanism on Ni catalyst

The present work investigated the possibility of the formation of graphene interconnects and studied the behavior of graphene growth in wiring structure. Graphene nucleated on the facet of catalytic metal, and multi layer graphene grew along the terrace surface of catalytic metal. Selective graphene growth served the stacked interconnects structure of graphene / Ni catalytic metal.

Control of Resistance by Oxide on the Surface of Cu Interconnects With CuSiN and Ti-based Barrier Metal

To achieve both low line resistance and high electromigration (EM) reliability, CuSiN was formed on CuxO, which was purposely left on the Cu interconnect. Oxide on the Cu surface effectively suppressed Si diffusion into the Cu line: this diffusion had, in the absence of the oxide, appeared during CuSiN formation and increased line resistance. EM reliability, however, was degraded in the case of Ta barrier metal (BM). The degradation occurred because the number of Cu-Si bonds decreased, and the number of Si-O bonds increased. To counteract this, Ti-based BM was used in combination with CuSiN formed on CuxO [CuSiN(Cux O)], because Ti is uniformly distributed in Cu grain boundaries on the Cu surface when Ti is used together with CuSiN, and Ti oxide is preferentially formed to Si oxide. As a result, the combination of CuSiN(CuxO) and Ti-based BM successfully retained the EM improvement brought about by CuSiN, whereas line resistance remained low. We have found a new solution that achieves compatibility between low line resistance and high EM reliability with ease by forming CuSiN on a CuxO surface rather than by performing a sensitive adjustment of CuSiN formation.