Hirotsugu Kojima

Half-swing clocking scheme for 75% power saving in clocking circuitry

Introduction Recently, reducing power consumption without sacrificing processing speed, is a critical factor in LSI design, especially for hand-held devices. It has been thought that the power consumed by the clocking circuitry takes a large portion of the total power in digital LSI. We disclose here that 33% of the power is consumed by the clocking in an adaptive equalizer[l]. In a microprocessor[2], we estimate that 35% of the power is consumed by clocking. This is because clock frequency is usually several times higher than other signals. It is well-known that reducing supply voltage gives us significant power savings at the expense of speed[3]. The operation of two stacked DRAM circuits at half the supply voltage was proposed[4]. However, this technology pays the penalty of reduced speed, since each DRAM works with half the supply voltage. We propose a new clocking scheme in which the supply voltage only for the clock driver is reduced to half of the LSI supply voltage, and the entire clock loads are driven by a half swing clock. This technology allows us to reduce clocking power consumption by 75%. The degradation in speed is very small because the random logic circuits in the critical path are still supplied by the full voltage. The key to the proposed clocking scheme is the concept that the voltage is reduced only for clocking circuitry. This results in great power reduction with minimal degradation in speed.

Data-dependent logic swing internal bus architecture for ultralow-power LSI's

A reduced-swing internal bus scheme is proposed for achieving ultralow-power LSIs. The proposed data-dependent logic swing bus (DDL bus) uses charge sharing between bus wires and an additional bus wire to reduce its voltage swing. With this technique, the power dissipation of the proposed bus is reduced to 1/16 that of a conventional bus when used for a 16-b-wide bus. In addition, a dual-reference sense-amplifying receiver (DRSA receiver) has been developed to convert a reduced-swing bus signal to a CMOS-level signal without loss of noise margin or speed. Experimental circuits fabricated using 0.5-/spl mu/m CMOS process verify the low-power operation of the proposed bus at an operating frequency of 40 MHz with a supply voltage of 3.3 V. >

Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer

This paper presents a new pipeline structure that dramatically reduces the power consumption of multimedia processors by using the commonly observed characteristic that most of the execution cycles of signal processing programs are used for loop executions. In our pipeline, the signals obtained by decoding the instructions included in a loop are temporarily stored in a small-capacity RAM that we call decoded instruction buffer (DIB), and are reused at every cycle of the loop iterations. The power saving is achieved by stopping the instruction fetch and decode stages of the processor during the loop execution except its first iteration. The result of our power analysis shows that about 40% power saving can be achieved when our pipeline structure is incorporated into a digital signal processor or RISC processor. The area of the DIB is estimated to be about 0.7 mm/sup 2/ assuming triple-metal 0.5 /spl mu/m CMOS technology.

Power analysis of a programmable DSP for architecture/program optimization

Power consumption has become one of the primary metrics in CMOS LSI design. A high level power estimation model will be indispensable to evaluate architectures and programming styles for performance and power consumption optimization. A model was proposed in which a constant energy was used for every module but data dependency was not taken into account. The purpose of this paper is to quantify the module break down and the data dependency of the power consumption and to find a key for high level power estimation. We analyzed power consumption of a 24 bit fixed point DSP, HX24, which we developed previously. We have found that the buses do not consume as much power as we originally expected while the data operation modules consume much power and the data dependency caused about 30% variation in worst case chip power. This is the first paper that describes how large the data dependency of data operation is and how low the bus power consumption is in a DSP of an extended Harvard architecture.

A 20-ns CMOS micro DSP core for video-signal processing

A programmable 8-b digital signal processor core with an instruction cycle time of 20 ns is developed. A 37.5-mm chip is fabricated by advanced 1.0- mu m double-level-metal CMOS technology. This processor has a reconfigurable high-speed data path supporting several multiply/accumulate function, including 16-tap linear-phase transversal filtering, high-speed adaptive filtering, and eight-point discrete cosine transformation. To provide high-speed operation within the chip, a programmable phase-locked loop circuit is built on the chip. This circuit generates a high-speed clock, which is a multiple of the system clock fed from outside, and is synchronized to the system clock. >

Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSP

While power consumption has become an important design constraint very few reports of power analysis of processors are available in the literature. The processor considered is an experimental integration of a 16-bit DSP and a 32-bit RISC microcontroller, ERDI. Simulation based power analysis on a back annotated design is used to obtain data for a set of DSP application kernels and synthetic benchmarks.

Data-Dependent Logic Swing Internal Bus Architecture for Ultra-Low-Power Lsis

A reduced-swing internal bus scheme is proposed for achieving ultralow-power LSIs. The proposed data-dependent logic swing bus (DDL bus) uses charge sharing between bus wires and an additional bus wire to reduce its voltage swing. With this technique, the power dissipation of the proposed bus is reduced to 1/16 that of a conventional bus when used for a 16-b-wide bus. In addition, a dual-reference sense-amplifying receiver (DRSA receiver) has been developed to convert a reduced-swing bus signal to a CMOS-level signal without loss of noise margin or speed. Experimental circuits fabricated using 0.5-μm CMOS process verify the low-power operation of the proposed bus at an operating frequency of 40 MHz with a supply voltage of 3.3 V