Mitsuru Hiraki

Data-dependent logic swing internal bus architecture for ultralow-power LSI's

A reduced-swing internal bus scheme is proposed for achieving ultralow-power LSIs. The proposed data-dependent logic swing bus (DDL bus) uses charge sharing between bus wires and an additional bus wire to reduce its voltage swing. With this technique, the power dissipation of the proposed bus is reduced to 1/16 that of a conventional bus when used for a 16-b-wide bus. In addition, a dual-reference sense-amplifying receiver (DRSA receiver) has been developed to convert a reduced-swing bus signal to a CMOS-level signal without loss of noise margin or speed. Experimental circuits fabricated using 0.5-/spl mu/m CMOS process verify the low-power operation of the proposed bus at an operating frequency of 40 MHz with a supply voltage of 3.3 V. >

A 1.5-V full-swing BiCMOS logic circuit

A BiCMOS logic circuit applicable to sub-2-V digital circuits has been developed. A transiently saturated full-swing BiCMOS (TS-FS-BiCMOS) logic circuit operates twice as fast as CMOS at 1.5-V supply. A newly developed transient-saturation technique, with which bipolar transistors saturate only during switching periods, is the key to sub-2-V operation because a high-speed full-swing operation is achieved to remove the voltage loss due to the base-emitter turn-on voltage. Both small load dependence and small fan-in dependence of gate delay time are attained with this technique. A two-input gate fabricated with 0.3- mu m BiCMOS technology verifies the performance advantage of TS-FS-BiCMOS over other BiCMOS circuits and CMOS at sub 2-V supply. >

Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer

This paper presents a new pipeline structure that dramatically reduces the power consumption of multimedia processors by using the commonly observed characteristic that most of the execution cycles of signal processing programs are used for loop executions. In our pipeline, the signals obtained by decoding the instructions included in a loop are temporarily stored in a small-capacity RAM that we call decoded instruction buffer (DIB), and are reused at every cycle of the loop iterations. The power saving is achieved by stopping the instruction fetch and decode stages of the processor during the loop execution except its first iteration. The result of our power analysis shows that about 40% power saving can be achieved when our pipeline structure is incorporated into a digital signal processor or RISC processor. The area of the DIB is estimated to be about 0.7 mm/sup 2/ assuming triple-metal 0.5 /spl mu/m CMOS technology.

A 512 kB MONOS type flash memory module embedded in a microcontroller

We present a 512 kB MONOS type flash memory module embedded in a microcontroller fabricated with a 0.18 /spl mu/m CMOS process. Our new memory cell structure enables the whole read path in the module to be composed of low voltage transistors that are the same as those used in the CPU core, and therefore achieves compact layout of peripheral circuits. The module achieves 34 MHz random access read operation. The measured program time and erase time for a 64 kB block were less than 4 ms and less than 11 ms, respectively. The area of the 512 kB module is 5.4 mm/sup 2/.

Quasi-complementary BiCMOS for sub-3-V digital circuits

The authors describe a quasi-complementary BiCMOS (QC-BiCMOS) circuit scheme for the low-supply-voltage deep-submicrometer regime. A QC-BiCMOS performs twice as fast as a CMOS even at a 2.5-V supply without a p-n-p bipolar transistor. Key circuits for this low-voltage performance are a separation between the base of the pull-up bipolar and the base of a quasi-p-n-p and the carefully designed base discharging circuit. A quasi-p-n-p combination of a pMOS and an n-p-n bipolar based on these circuits shows an equivalent cutoff frequency of over 10 GHz. The delay expressions for the QC-BiCMOS are analyzed and compared with the conventional BiCMOS. A 0.3- mu m fully loaded three-input NAND gate was fabricated, verifying that the QC-BiCMOS has more than twice the performance leverage over the conventional BiCMOS and the CMOS at a sub-3-V supply. >

Pass transistor based gate array architecture

This paper describes a completely new gate array architecture that fully exploits inherent advantages of pass transistor logic which a conventional architecture can not. In implementing SRAMs, our gate array achieves a 1.5 times higher density than a conventional gate array due to its different size transistors in the basic cell. An 8/spl times/8 b multiplier designed with this gate array using 0.4-/spl mu/m CMOS process achieves a multiplication time of 12.7 ns and dissipates 480 /spl mu/W with the supply voltage of 1.2 V. A 1.2 V 9 ns 1 kb SRAM was also designed with the same gate array.

A 63-/spl mu/W standby power microcontroller with on-chip hybrid regulator scheme

We present a 32-bit RISC microcontroller having an on-chip DC/DC converter. The chip standby power including the DC/DC converter is reduced to 63 /spl mu/W with a new hybrid regulator scheme in which the microcontroller selects a switching regulator in active mode and a series regulator in standby mode. The achieved standby power corresponds to only about 1% the standby power with a conventional scheme which always uses a switching regulator.

1.2 V mixed analog/digital circuits using 0.3 /spl mu/m CMOS LSI technology

Although dropping the supply voltage below 2 V is effective in reducing power consumption of LSIs for low-power systems, it has not been adopted because it severely degrades the system performance. This paper reports an experimental 1.2 V mixed analog/digital LSI based on 0.3 /spl mu/m laterally-doped buried-layer (LDB) CMOS with /spl plusmn/0.4 V threshold voltages. Based on circuits such as a double feedforward phase-compensated amplifier and a self current cut-off sense amplifier, a 9b 2 MHz 4 mW pipelined A/D converter, a 16 kb 2 mW SRAM with 32 ns access time, and a basic logic gate with a 400 ps delay and 0.4 /spl mu/W/MHz dissipation are realized.<<ETX>>

A 1000 MIPS BiCMOS microprocessor with superscalar architecture

A 1000 MIPS computer, integrated on a single chip and experimentally developed using 0.3- mu m self-aligned BiCMOS technology, is described. It features superscalar processing and pipelined access of interleaved secondary cache. The authors describe circuit techniques of the cache, TLB, register, file, and ALU (arithmetic and logic unit) operating at 250 MHz.<<ETX>>

On-chip multiple superscalar processors with secondary cache memories

The development of an experimental high-performance microprocessor chip based on a 0.3- mu m BiCMOS technology is discussed. It is designed to operate at a 250-MHz clock rate. It includes two processors, each of which executes two instructions in parallel. The chip performs 1000 MIPS when instructions and data are fetched from primary caches. It also includes a four-wave interleaved secondary cache assessed in parallel according to a split-bus protocol, to reduce shared memory conflicts. The VLSI architecture and design results of this chip are described.<<ETX>>