Katsuro Sasaki

A 1.5-ns 32-b CMOS ALU in double pass-transistor logic

Describes circuit techniques for fabricating a high-speed adder using pass-transistor logic. Double pass-transistor logic (DPL) is shown to improve circuit performance at reduced supply voltage. Its symmetrical arrangement and double-transmission characteristics improve the gate speed without increasing the input capacitance. A carry propagation circuit technique called conditional carry selection (CCS) is shown to resolve the problem of series-connected pass transistors in the carry propagation path. By combining these techniques, the addition time of a 32-b ALU can be reduced by 30% from that of an ordinary CMOS ALU. A 32-b ALU test chip is fabricated in 0.25- mu m CMOS technology using these circuit techniques and is capable of an addition time of 1.5 ns at a supply voltage of 2.5 V. >

A 4.4 ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexer

A 54/spl times/54-b multiplier using pass-transistor multiplexers has been fabricated by 0.25 /spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry lookahead adder (CLA), both featuring pass-transistor multiplexers, have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77/spl times/3.41 mm. The multiplication time is 4.4 ns at a 3.5-V power supply. >

Half-swing clocking scheme for 75% power saving in clocking circuitry

Introduction Recently, reducing power consumption without sacrificing processing speed, is a critical factor in LSI design, especially for hand-held devices. It has been thought that the power consumed by the clocking circuitry takes a large portion of the total power in digital LSI. We disclose here that 33% of the power is consumed by the clocking in an adaptive equalizer[l]. In a microprocessor[2], we estimate that 35% of the power is consumed by clocking. This is because clock frequency is usually several times higher than other signals. It is well-known that reducing supply voltage gives us significant power savings at the expense of speed[3]. The operation of two stacked DRAM circuits at half the supply voltage was proposed[4]. However, this technology pays the penalty of reduced speed, since each DRAM works with half the supply voltage. We propose a new clocking scheme in which the supply voltage only for the clock driver is reduced to half of the LSI supply voltage, and the entire clock loads are driven by a half swing clock. This technology allows us to reduce clocking power consumption by 75%. The degradation in speed is very small because the random logic circuits in the critical path are still supplied by the full voltage. The key to the proposed clocking scheme is the concept that the voltage is reduced only for clocking circuitry. This results in great power reduction with minimal degradation in speed.

A 7-ns 140-mW 1-Mb CMOS SRAM with current sense amplifier

A 7-ns 140-mW 1-Mb CMOS SRAM was developed to provide fast access and low power dissipation by using high-speed circuits for a 3-V power supply: a current-sense amplifier and pre-output buffer. The current-sense amplifier shows three times the gain of a conventional voltage-sense amplifier and saves 60% of power dissipation while maintaining a very short sensing delay. The pre-output buffer reduces output delays by 0.5 ns to 0.75 ns. The 6.6- mu m/sup 2/ high-density memory cell uses a parallel transistor layout and phase-shifting photolithography. The critical charge that brings about soft error in a memory cell can be drastically increased by adjusting the resistances of poly-PMOS gate electrodes. This can be done without increasing process complexity or memory cell area. The 1-Mb SRAM was fabricated using 0.3- mu m CMOS quadrupole-poly and double-metal technology. The chip measures 3.96 mm*7.4 mm (29 mm/sup 2/). >

A voltage down converter with submicroampere standby current for low-power static RAMs

A submicroampere standby current voltage downconverter (VDC) for high-density, low-power static RAMs is described. The current consumption of the VDC in standby mode can be decreased by using a novel low-current and temperature-independent current source circuit. The total current is less than 0.5 mu A at external voltage ranging from 3 to 5 V and at temperatures ranging from -20 to 80 degrees C. The voltage-follower circuits for standby and operation modes are stable despite the low current consumption in the standby mode. The phase margin of the voltage follower for standby mode is 50 degrees , and that for operation mode is 90 degrees . This indicates that the VDC is a promising circuit for battery-backup and high-density static RAMs. >

A 1-V TFT-load SRAM using a two-step word-voltage method

A 1-V battery-operated SRAM with a 10.2- mu m/sup 2/ TFT (thin-film transistor) load cell is described which uses a two-step word-voltage (TSW) method, a level-shift sense amplifier, and a 0.23- mu A boosted-level generator. By using these means, a 0.7- mu A-standby-current 4-Mb SRAM with 75-mm/sup 2/ chip can be installed in a terminal using a single 1.2-V battery. The measured currents and output voltages of the boosted-level generator in the standby model are shown, and the characteristics of a 4-kB test chip fabricated using a 0.4- mu m CMOS technology are listed along with the process parameters. Operating waveforms of the 4-kb SRAM are shown. >

A 4.4-ns CMOS 54/spl times/54-b multiplier using pass-transistor multiplexer

A 54/spl times/54-b multiplier using pass-transistor multiplexer has been fabricated by 0.25-/spl mu/m CMOS technology. To enhance the speed performance, a new 4-2 compressor and a carry look-ahead adder (CLA) both featuring the use of pass-transistor multiplexers have been developed. The new circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages is minimized due to the high logic functionality of pass-transistor multiplexers. The active size of the 54/spl times/54-b multiplier is 3.77 mm/spl times/3.41 mm. The multiplication time is 4.4 ns at 2.5 V power supply.<<ETX>>

Stage-skip pipeline: a low power processor architecture using a decoded instruction buffer

This paper presents a new pipeline structure that dramatically reduces the power consumption of multimedia processors by using the commonly observed characteristic that most of the execution cycles of signal processing programs are used for loop executions. In our pipeline, the signals obtained by decoding the instructions included in a loop are temporarily stored in a small-capacity RAM that we call decoded instruction buffer (DIB), and are reused at every cycle of the loop iterations. The power saving is achieved by stopping the instruction fetch and decode stages of the processor during the loop execution except its first iteration. The result of our power analysis shows that about 40% power saving can be achieved when our pipeline structure is incorporated into a digital signal processor or RISC processor. The area of the DIB is estimated to be about 0.7 mm/sup 2/ assuming triple-metal 0.5 /spl mu/m CMOS technology.

Power analysis of a programmable DSP for architecture/program optimization

Power consumption has become one of the primary metrics in CMOS LSI design. A high level power estimation model will be indispensable to evaluate architectures and programming styles for performance and power consumption optimization. A model was proposed in which a constant energy was used for every module but data dependency was not taken into account. The purpose of this paper is to quantify the module break down and the data dependency of the power consumption and to find a key for high level power estimation. We analyzed power consumption of a 24 bit fixed point DSP, HX24, which we developed previously. We have found that the buses do not consume as much power as we originally expected while the data operation modules consume much power and the data dependency caused about 30% variation in worst case chip power. This is the first paper that describes how large the data dependency of data operation is and how low the bus power consumption is in a DSP of an extended Harvard architecture.

A 12.5-ns 16-Mb CMOS SRAM with common-centroid-geometry-layout sense amplifiers

A 16-Mb CMOS SRAM using 0.4-/spl mu/m CMOS technology has been developed. This SRAM features common-centroid-geometry (CCG) layout sense amplifiers which shorten the access time by 2.4 ns. A flexible redundancy technique achieves high efficiency without any access penalty. A memory cell with stacked capacitors is fabricated for high soft-error immunity. A 16-Mb SRAM with a chip size of 215 mm/sup 2/ is fabricated and an address access time of 12.5 ns has been achieved. >