Hiroyuki Morinaka

An 8.8-ns 54/spl times/54-bit multiplier with high speed redundant binary architecture

A high speed redundant binary (RB) architecture, which is optimized for the fast CMOS parallel multiplier, is developed. This architecture enables one to convert a pair of partial products in normal binary (NB) form to one RE number with no additional circuit. We improved the RB adder (RBA) circuit so that it can make a fast addition of the RB partial products. We also simplified the converter circuit that converts the final RE number into the corresponding NE number. The carry propagation path of the converter circuit is carried out with only multiplexer circuits. A 54/spl times/54-bit multiplier is designed with this architecture. It is fabricated by 0.5 /spl mu/m CMOS with triple level metal technology. The active area size is 3.0/spl times/3.08 mm/sup 2/ and the number of transistors is 78,800. This is the smallest number for all 54/spl times/54-bit multipliers ever reported. Under the condition of 3.3 V supply voltage, the chip achieves 8.8 ns multiplication time. The power dissipation of 540 mW is estimated for the operating frequency of 100 MHz. These are, so far, the fastest speed and the lowest power for 54/spl times/54-bit multipliers with 0.5-/spl mu/m CMOS.

A 64 bit carry look-ahead CMOS adder using Modified Carry Select

We present a 64 b Carry Look-ahead (CLA) adder having a 2.6 ns delay time at 3.3 V power supply within 0.27 mm/sup 2/ using a 0.5 /spl mu/m CMOS technology. We derived its structure from considering the tradeoffs between speed and area. This consideration includes not only the gate intrinsic delay but also the wiring delay and the gate capacitance delay. Moreover we introduced a new carry select scheme called Modified Carry Select (MCS). MCS has 20% area advantage over the conventional Carry Select Adder (CSA).

An HDTV Video Decoder IC For ATV Receivers

An HDTV video decoder IC for ATV receivers is presented. Its dual decoder architecture supports MPEG-2 MP@HL (62,668,800 display samples per second) and an SDRAM memory bandwidth of 6.5 gigabits per second.

Leading-zero anticipatory logic for high-speed floating point addition

This paper describes new Leading-Zero Anticipatory (LZA) Logic for high-speed floating-point addition (FADD). This method carries out the pre-decoding for the normalization concurrently with the addition for significand. Besides, it performs the shift operation in parallel with the rounding operation. The proposed logic consists of the simple circuit with 1.8% penalty in transistor count. The FADD core using the proposed logic operates at 160 MHz, where the core has been fabricated with 0.5 /spl mu/m CMOS technology with triple metal interconnections.

A 286 MHz 64-bit floating point multiplier with enhanced CG operation

High speed floating point (FP) multipliers are essential for high speed calculation systems because increasingly large numbers of FP multiplications must be carried out in various applications such as scientific calculation and computer graphics (CG). CG, in particular, requires enormous amount of FP multiplications to obtain high quality images required for multimedia systems. To realize high speed, the critical path delay must be minimized. In this paper, we discuss a method to shorten the delay time of the critical path. Then we present an FP multiplier design based on the method. A special function for CG is also implemented without increasing the critical path delay. Finally, we show the fabrication and test results of the FP multiplier.