Tadashi Sumi

A 1.9 GHz single-chip IF transceiver for digital cordless phones

Portable communication equipment, such as cellular phones and digital cordless phones, employ as many ICs as possible instead of discrete devices to be competitive in size, weight, and power dissipation. Although a UHF single-chip transceiver has been reported, it is still difficult to achieve that integration level for L-band cordless phones, such as the Personal Handy Phone System (PHS). This article describes a 1.9 GHz single chip IF transceiver IC for digital-cordless phones.

A Display Processor Conforming To All ATV Formats With 188-tap FIR Filters And 284 Kb FIFO Memories

To achieve a single chip solution for a display processor conforming to all DTV formats, various hardwired approaches such as the write end toggle signal (WETS) based design technique and dynamic voltage sensing FIFO architecture have been developed. As a result, all functions including macroblock-to-raster conversion, frame/filed rate conversion, scan format conversion, and ordinary picture making functions such as color interpolation, enhancement, inverse matrix, on screen display, and D/A conversion have been successfully integrated into a single chip. The display processor has a total memory capacity of 284 Kb and filters with a total of 188 taps in an area of 14.9 mm/spl times/14.9 mm. It was fabricated in 0.5 um CMOS technology with 2-metal.

A multilevel QAM demodulator VLSI with wideband carrier recovery and dual equalizing mode

A 4-/16-/64-/256-QAM demodulator LSI with an all-digital carrier-recovery loop including a novel phase detector and a fractionally-/ symbol-spaced equalizer is described. The phase detector, deciding the transmitted symbol from received signal power, detects the phase error up to ±45° and enables the loop to internally eliminate the ±80 KHz carrier-frequency offset. The fractionally-spaced equalizer is implemented at the same clock rate as the symbol-spaced equalizer by only increasing the selectors and flip-flops, though the former theoretically requires a two times faster operation than the latter. An LSI operating at a symbol rate up to 8 MBaud is successfully implemented.

An HDTV Video Decoder IC For ATV Receivers

An HDTV video decoder IC for ATV receivers is presented. Its dual decoder architecture supports MPEG-2 MP@HL (62,668,800 display samples per second) and an SDRAM memory bandwidth of 6.5 gigabits per second.

An area efficient hardware sharing filter generator suitable for multiple video format conversions

A software program which automatically generates area-efficient circuits for multiple video format conversion filters by using new hardware sharing technique has been developed. The circuits employing this new technique share most of hardware between all filters by utilizing the feature that these filters never operate at the same time. Its performance has been demonstrated by applying the technique to an LSI which converts formats such as NTSC and SDTV for plural types of HDTV monitor. The number of gates for all filters in this chip was decreased from 99,053 to 23,833 by the software program. As a result, all the hardware was successfully integrated into a single chip.

14.4: LCD Addressed Photo ‐ Printer System

A Liquid crystal display addressed photo-printer system that prints an image of the display directly on instant-photo-film is proposed. Two types of optical systems, a collimating backlight system and a 2-dimensional microlens array system, are examined. A 200 ppi (4 lp/mm)liquid crystal display image can be printed by this novel optical system.

Static linearity error analysis of subranging A/D converters

An 8- to 10-bit CMOS A/D converter with a conversion rate of more than 16 megasample/second is required in consumer video systems. Subranging architecture is widely used to realize such A/D converters. This architecture, however, exhibits a reference voltage error caused by resistor ladder loadings. The error has been discussed with respect to a flash A/D converter by Dingwall. However, it can not be applied for a subranging A/D converter as it is. The analysis of this error is very important in realizing the desired accuracy of a subranging A/D converter. This paper describes a static analysis to improve the linearity, and reports the results of this analysis for two typical types, one with individual comparator arrays for coarse and fine A/D conversions, and the other with the same comparator array for both conversions. This analysis makes it clear that a subranging A/D converter has unique saw-tooth characteristic in fine linearity errors. Furthermore, this analysis clarifies what conditions are necessary to achieve the desired accuracy. It is necessary, for example, that the product of the total input capacitance of the comparators C, the conversion rate fsand the total ladder resistance R is less than 0.03 in A/D converters with individual comparator arrays and 0.016 in A/D converters with the same comparator array in order to achieve 10-bit accuracy.