Shozo Hirano

Dynamic power-supply and well noise measurement and analysis for high frequency body-biased circuits

Dynamic noises on power-supply as well as multiple wells necessary for body-biased circuits show frequency components strongly characterized by the interaction of circuit operation and AC transfer of biasing networks. Measurements with the resolution of 100-ps and 100-uV for a few 100-ns and 1-V ranges on multiple points in a product register file are performed at various operating frequencies up to 400 MHz and show the noises clearly emphasized in frequency domain by the interaction. A proposed analysis flow recruiting a fast SPICE simulator and parasitic extractors can predict the dynamic noises due to combined power supply, ground, well, and substrate interactions, and provide robustness to the design of body-bias control circuitry.

Power-Supply Noise Reduction with Design for Manufacturability

In the move toward higher clock rates and advanced process technologies, designers of the latest electronic products are finding increasing silicon failure with respect to noise. On the other hand, the minimum dimension of patterns on LSIs is much smaller than the wavelength of exposure, making it difficult for LSI manufacturers to obtain high yield. In this paper, we present a solution to reduce power-supply noise in LSI microchips. The proposed design methodology also considers design for manufacturability (DFM) at the same time as power integrity. The method was successfully applied to the design of a system-on-chip (SOC), achieving a 13.1--13.2% noise reduction in power-supply voltage and uniformity of pattern density for chemical mechanical polishing (CMP).

Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits

Dynamic power supply noise measurements with resolutions of 100 ps and 100μV for 100 ns and 1 V ranges are performed at various operating frequencies up to 400 MHz on multiple points in a low power register file and SRAM for product chips by using on-chip noise detectors. The measurements show that the noises are clearly emphasized in frequency domains by the interaction of circuit operations and bias networks AC transfers. A proposed design methodology that covers a fast SPICE simulator and parasitic extractors can predict dynamic noises from power supplies, ground, well, and substrate interactions to provide robustness to the design of low power body bias control circuitry.

A design methodology for low EMI-noise microprocessor with accurate estimation-reduction-verification

The main objective of our work is to develop a fast and accurate total solution for dramatically reducing electromagnetic interference (EMI) noise in high-performance LSI microchips at the design stage through unifying estimation, reduction, and verification. This innovative methodology has been proven in the successful design of a 32-bit microprocessor with very low EMI noise.