Hisakazu Iizuka

An optimally designed process for submicrometer MOSFET's

An n-channel MOS process has been optimized to yield desirable characteristics for submicrometer channel-length, MOSFETs. Process/device simulation is extensively used to find an optimized processing sequence compatible with typical production-line processes. The simulation results show an excellent agreement with experimental data. We have obtained long-channel subthreshold characteristics, saturation drain characteristics up to 5 V, and a minimized substrate bias sensitivity for transistors with channel lengths as small as 0.5 µm. The short-channel effects have been also minimized. A new self-aligned silicidation technology has been developed to reduce the increased resistance of diffused layers with down-scaled junction depths.

A simplified box (buried-oxide) isolation technology for megabit dynamic memories

A simplified version of BOX isolation technology is described. The new process has been greatly simplified over the original BOX by introducing an additional non-critical masking step. The body effect observed in narrow channel devices is reduced in the new structure. The capacitance measurement on diffused junctions in BOX structure shows smaller contributions from diode perimeter as compared to LOCOS structure. Hot electron reliability of small geometry MOSFETs has been also studied and the results are presented and discussed.

An optimally designed process for submicron MOSFETs

An n-channel MOS process has been optimized to yield desirable characteristics for submicron channel length MOSFETs. Process/device simulation is extensively used to find an optimized processing sequence compatible to typical production line processes. The simulation results show an excellent agreement to experimental data. We have obtained long-channel subthreshold characteristics, saturation drain characteristics up to 5V, and minimized substrate bias effects for transistors with channel lengths as small as 0.5µ. The short channel effects have been also minimized. A unique self-aligned silicidation technology which has been developed to reduce the increased resistance of down-scaled junctions is also presented.

Limiting factors for programming EPROM of reduced dimensions

In order to realize high density EPROMs it is necessary to reduce the dimensions of EPROM cells. In this paper the programming characteristics of the floating gate EPROMs are discussed in relation to the limiting factors for device parameters and the programming conditions. Some problems which arise from the arrayed cell configuration are clarified. The programming speed of an EPROM is remarkably lowered by the voltage drop in a bit line due to an excess current flow through deselected cells which is induced by pulling up of the floating gate potential due to capacitance coupling between the bit line and the floating gate. A punch-through current in memory cells has the same effect on the programming characteristics. The feasibility of higher density EPROMs are also discussed by taking these problems into account.

Characterization of two step impact ionization and its influence in NMOS and PMOS VLSI's

Two step impact ionization phenomena near the high electric field drain region are characterized, both theoretically and experimentally, in small geometry NMOS and PMOS structures. Influences of primary and secondary impact ionized carrier flows are quantitatively considered as design constraints in high density MOS memories, more specifically for CMOS devices and also for poly-Si resistor load RAM cells.

Optimum design of dual-control gate cell for high-density EEPROM's

A new floating-gate-type cell with a dual-control gate (dc cell) has been developed and the structure optimized to realize high-density EEPROMs. In this new cell, an address selection transistor has been eliminated, thus attaining a single-transistor-per-cell configuration. The address selection is achieved by coincidence of two control gates, which are connected to column or row decoders supplied with an appropriate programming voltage. The stored charge in the floating gate suffers some disturbance by repetition of half-selection mode operation--defined as a state in which one of the control gates is set to high and the other to low during programming. In order to improve the endurance of the cell against half-selection mode operation, a new source biasing method has been introduced. As a result, the endurance has been improved by more than 3 orders of magnitude. A WRITE/ERASE endurance of 105cycles and a data retention capability of more than 10 years have been obtained for the dc cell. The design parameters for a 64K EEPROM chip are also described.

A two-dimensional computer simulation of hot carrier effects in MOSFETs

Substrate and gate injection currents due to impact ionization are calculated using a newly developed total simulator. The model for these currents includes the introduction of a new injection criterion for electrons to account for the observed discrepancy between measurement and calculation based on previous models. Good agreement with measurement is obtained for both currents. The model is also applied to the estimation of threshold voltage shifts in scaled down MOSFETs and unintentional writings of EPROM cells.

Design Limitations due to Substrate Currents and Secondary Impact lonization Electrons in NMOS LSI's

A quantitative analysis of the substrate current and its secondary effects in NMOS LSIs are described. The substrate current is accurately calculated by a two-dimensional numerical analysis for short channel transistors down to 1 µm channel length. Minority carrier injection in substrate, which results from a secondary impact ionization, is also studied. The minority carrier current in the substrate is measured using a CCD test device, and is found to be nearly proportional to the substrate current. A physical model for these phenomena is also presented. Minority carrier injection efficiency is then given by an empirical equation as a function of effective channel length. Based on the models and experimental results, limiting voltages for MOS LSIs are estimated in terms of punch-through, parasitic bipolar transistor breakdown, excess electrons and hot electron trapping.

A New Field Isolation Technology for High Density MOS LSI

A unique field isolation technology has been developed for n-channel MOS LSIs in which the HF gas reverse etching of oxide was utilized. This new technology essentially eliminates several disadvantages of the widely used coplanar (also known as LOCOS) technology. The field oxide delineation without birds beak, the lateral oxidation under the nitride mask, increases the packing density by about 43% and 55% for 4 µ and 3 µ design rules, respectively. Undesirable lateral diffusion of impurities during field oxidation is also greatly reduced in the new technology. Test devices and LSIs were fabricated and tested. The feasibility as a LSI process was successfully verified with the 16-bit microprocessor chip of TOSBAC 40L.

(Invited) Non-Thermal Carrier Generation in MOS Structures

Influence of generated carriers originated by hot electrons and radiations is described in MOS structures. A holding time degradation in a dynamic RAM is first presented with the two-step impact-ionization model, which is verified by a series of experiments. The impact ionization rate in the high electric field near the drain is also calculated by a two dimensional analysis, which leads to an accurate substrate current estimation. Effects of hot electron injection into the gate oxide, and of trapping are then studied utilizing a stacked gate MOS structure. From those results, design constraints in small geometry MOS LSIs are discussed.