J. Matsunaga

A low power 46 ns 256 kbit CMOS static RAM with dynamic double word line

A fast, low-power 32K/spl times/8-bit CMOS static RAM with a high-resistive polyload 4-transistor cell has been developed utilizing a dynamic double word line (DDWL) scheme. This scheme combines an automatic power down circuitry and double word line structure. The DDWL, together with bit line and sense line equilibration, reduces the core area delay time and operating power to about 1/2 and 1/15 that of a conventional device, respectively. A newly developed fault-tolerant circuitry improves fabrication yield without degrading the access time. As for a fabrication process, an advanced 1.2-/spl mu/m p-well CMOS technology is developed to realize the ULSI RAM, integrating 1,600,000 elements on a 6.68/spl times/8.86 mm/SUP 2/ chip. The RAM offers, typically, 46 ns access time, 10 mW operating power and 30 /spl mu/W standby power.

1-Mbit virtually static RAM

The 1-Mb RAM utilizes a one-transistor, one-capacitor dynamic memory cell. Since all the refresh-related operations are done on chip, the RAM acts as a virtually static RAM (VSRAM). The refresh operations are merged into the normal operation, called a background refresh, the main feature of the VSRAM. Since the fast operation of the core part of the RAM is crucial to minimize the access-time overhead by the background refresh, 16 divided bit lines and parallel processing techniques are utilized. Novel hot-carrier resistant circuits are applied selectively to bootstrapped nodes for high hot-carrier reliability. N-channel memory cells are embedded in a p-well, which gives a low soft error rate of less than 10 FIT. 1-/spl mu/m NMOSFETs with moderately lightly doped drain structures offer fast 5-V operation with sufficient reliability. An advanced double-level poly-Si and double-level Al twin-well CMOS technology is developed for fast circuit speed and high packing density. The memory cell size is 3.5/spl times/8.4 /spl mu/m/SUP 2/, and the chip size is 5.99/spl times/13.8 mm./SUP 2/. Address access time is typically 62 ns, with 21-mA operating current and 30-/spl mu/A standby current at room temperature.

0.5 V SOI CMOS pass-gate logic

Demand for low-power ULSIs for mobile electronic equipment is increasing rapidly. To reduce power consumption, lower operating voltage and minimized device size (or count) is essential. To lower the actual threshold voltage and lower the operation voltage, SOI MOSFET with gate-body connection is proposed. However, the circuit architecture that affords the maximum advantage of the body controlled SOI MOSFET has not yet been reported. The SOI CMOS pass-gate logic described here offers the lowest operation voltage and reduced transistor dimensions. In this logic the body of the SOI pass-gate is connected to the input signal given to the gate. Low threshold voltage for the onstate pass-gate and high threshold voltage for the off-state passgate is realized, and the increase in the threshold voltage due to the body-effect is suppressed. Two types of buffer suitable for SOI pass-gate logic are examined.

A 64Kb CMOS RAM

This report will cover the design of a fault-tolerant 8K×8b static RAM using a double polysilicon CMOS technology. Memory access is 70ns typically, while consuming 15mW operating power and 10μW standby power.

Evidence for impact‐ionized electron injection in substrate of n‐channel MOS structures

Impact‐ionization current during saturation mode operation is widely known in MOS devices. Although not noted in previous work, minority carriers also may be observed in the substrate, together with hole current. These minority carriers can degrade the MOS depletion layer lifetime, thus limiting the performance of MOS dynamic devices. A series of experiments utilizing the C‐t method, the MOS capacitor surface potential measurement, and the charge‐coupled device (CCD) is described, which provides evidence for electrically generated electrons in the substrate of n‐channel MOS structures.

Characterization of two step impact ionization and its influence in NMOS and PMOS VLSI's

Two step impact ionization phenomena near the high electric field drain region are characterized, both theoretically and experimentally, in small geometry NMOS and PMOS structures. Influences of primary and secondary impact ionized carrier flows are quantitatively considered as design constraints in high density MOS memories, more specifically for CMOS devices and also for poly-Si resistor load RAM cells.

A 25-ns 1-Mbit CMOS SRAM with loading-free bit lines

A 128 K/spl times/8-b CMOS SRAM is described which achieves a 25-ns access time, less than 40-mA active current at 10 MHz, and 2-/spl mu/A standby current. The novel bit-line circuitry (loading-free bit line), using two kinds of NMOSFETs with different threshold voltages, improves bit-line signal speed and integrity. The two-stage local amplification technique minimizes the data-line delay. The dynamic double-word-line scheme (DDWL) allows the cell array to be divided into 32 sections along the word-line direction without a huge increase in chip area. This allows the DDWL scheme to reduce the core-area delay time and operating power to about half that of other conventional structures. A double-metal 0.8-/spl mu/m twin-tub CMOS technology has been developed to realize the 5.6/spl times/9.5-/spl mu//SUP 2/ cell size and the 6.86/spl times/15.37-mm/SUP 2/ chip size.

Effects of silicon surface orientation on submicron CMOS devices

Effects of Si surface orientation on small dimension NMOS and PMOS characteristics at 300K and 77K have been experimentally investigated. Carrier transport in a high electric field and hot carrier-induced degradation have been examined in detail. In scaled NMOS devices alone, a triode channel transconductance depends strongly on Si surface orientation, but a pentode transconductance does not depend on it. These behaviors are qualitatively discussed with an effective mass model and carrier transport process. The Si surface orientation dependence of hot carrier-induced degradation is found to be related to the number of interface state. Based upon these results, the optimum surface orientation for submicron CMOS devices is discussed.

Directions in CMOS technology

This paper describes current status and future prospect of CMOS technology for VLSI circuit applications. Though requiring various improvements and optimizations, CMOS device structures and process steps remain to be rather conventional down to 1.2 µm, and real innovation or evolution is expected to come below 1.0 µm or in the sub-micron region. In that context, the authors review bulk CMOS technology from 2µm to sub-micron features based upon existing device characteristics, and also discuss directions for further downward scaling.

An 8-ns 1-Mbit ECL BiCMOS SRAM with double-latch ECL-to-CMOS-level converters

The design and performance of a high-speed 1 M*1-bit SRAM with ECL I/O are described. The 6.5*16.5-mm/sup 2/ chip was fabricated with a 0.8- mu m BiCMOS process technology. A modified double-word-line (MDWL) structure and a bit-line peripheral circuitry with normally-on bit-line equalization circuit are used to achieve high-speed read operation. The read speed is further enhanced by a novel ECL-to-CMOS-level converter with a double-latch configuration. The converter dissipates no DC current and contributes to low power consumption together with an automatic power-saving function, utilizing the address transition detection (ATD) technique. The access time is typically 8 ns, and the active power is 500 mW at 50 MHz. >