Susumu Kohyama

A Thermionic Electron Emission Model for Charge Retention in SAMOS Structure

Charge retention in SAMOS structures at elevated temperatures is effectively described by a thermionic electron emission model from a floating polysilicon gate into the surrounding oxide. Experimental results showed sufficiently good agreement with the theoretical model. The barrier height and collision frequency derived from the experiments are reasonable (1.24 eV and 2.5×104/sec, respectively). Long term data retention in floating gate EPROMs can also be predicted by this model.

Characterization of Polycrystalline Silicon MOS Transistors and Its Film Properties. I

The characterization of polycrystalline silicon MOS transistors and its film properties are studied, with special emphasis on the relationship between crystalline defects and carrier transport phenomena. An increase in mobility with gate field in polycrystalline silicon MOS transistors and also with doping concentration in polycrystalline silicon films is observed. These phenomena are interpreted as space charge scattering effects caused by a high density of dislocations in the films. U-shaped drain current vs gate voltage curves are observed both in p-channel and n-channel polycrystalline silicon MOS transistors. The anomalous drain current in the accumulation region is interpreted as junction breakdown at the drain edge caused by crystalline imperfections in the films.

Evidence for impact‐ionized electron injection in substrate of n‐channel MOS structures

Impact‐ionization current during saturation mode operation is widely known in MOS devices. Although not noted in previous work, minority carriers also may be observed in the substrate, together with hole current. These minority carriers can degrade the MOS depletion layer lifetime, thus limiting the performance of MOS dynamic devices. A series of experiments utilizing the C‐t method, the MOS capacitor surface potential measurement, and the charge‐coupled device (CCD) is described, which provides evidence for electrically generated electrons in the substrate of n‐channel MOS structures.

Method for manufacturing a semiconductor device having regions of different thermal conductivity

In gas phase growth of a polysilicon layer on a semiconductor substrate, a silicon layer of a single-crystal structure or a structure akin thereto may be formed only on an exposed surface of the substrate surrounded by an insulating film for element isolation by applying an energy beam to the substrate. A semiconductor device obtained by forming such an element as an MOS transistor on the silicon layer is free from any difference in level between an element region and an element isolation region, and hence from snapping or disconnection of any wiring traversing the boundary between those regions.

Characterization of two step impact ionization and its influence in NMOS and PMOS VLSI's

Two step impact ionization phenomena near the high electric field drain region are characterized, both theoretically and experimentally, in small geometry NMOS and PMOS structures. Influences of primary and secondary impact ionized carrier flows are quantitatively considered as design constraints in high density MOS memories, more specifically for CMOS devices and also for poly-Si resistor load RAM cells.

Directions in CMOS technology

This paper describes current status and future prospect of CMOS technology for VLSI circuit applications. Though requiring various improvements and optimizations, CMOS device structures and process steps remain to be rather conventional down to 1.2 µm, and real innovation or evolution is expected to come below 1.0 µm or in the sub-micron region. In that context, the authors review bulk CMOS technology from 2µm to sub-micron features based upon existing device characteristics, and also discuss directions for further downward scaling.

Selective polysilicon oxidation technology for defect free isolation

A new isolation technology is described for small geometry MOS LSIs in which selective polysilicon oxidation is utilized. In the process, a polysilicon film is deposited on a oxide layer grown on a silicon substrate, first. Thick thermal oxide is then selectively formed by polysilicon oxidation with a masking Si3N4film without pad oxide. The unoxidized polysilicon is etched off by a reactive ion etching, and then the residual polysilicon under the overhung oxide is oxidized for providing desired field oxide edge configuration. A test device was fabricated by this technology and the birds beak length was reduced to 0.15 µm, typically, in the case of no pad oxide. The feasibility of this technology for MOS VLSIs was confirmed without any serious process induced defects.

Design Limitations due to Substrate Currents and Secondary Impact lonization Electrons in NMOS LSI's

A quantitative analysis of the substrate current and its secondary effects in NMOS LSIs are described. The substrate current is accurately calculated by a two-dimensional numerical analysis for short channel transistors down to 1 µm channel length. Minority carrier injection in substrate, which results from a secondary impact ionization, is also studied. The minority carrier current in the substrate is measured using a CCD test device, and is found to be nearly proportional to the substrate current. A physical model for these phenomena is also presented. Minority carrier injection efficiency is then given by an empirical equation as a function of effective channel length. Based on the models and experimental results, limiting voltages for MOS LSIs are estimated in terms of punch-through, parasitic bipolar transistor breakdown, excess electrons and hot electron trapping.

A New Field Isolation Technology for High Density MOS LSI

A unique field isolation technology has been developed for n-channel MOS LSIs in which the HF gas reverse etching of oxide was utilized. This new technology essentially eliminates several disadvantages of the widely used coplanar (also known as LOCOS) technology. The field oxide delineation without birds beak, the lateral oxidation under the nitride mask, increases the packing density by about 43% and 55% for 4 µ and 3 µ design rules, respectively. Undesirable lateral diffusion of impurities during field oxidation is also greatly reduced in the new technology. Test devices and LSIs were fabricated and tested. The feasibility as a LSI process was successfully verified with the 16-bit microprocessor chip of TOSBAC 40L.

A 1.0µm N-well CMOS/Bipolar technology for VLSI circuits

This paper describes a 1.0um N-well CMOS/bipolar technology for VLSI analog-digital combined VLSI systems. With this technology, high performance CMOS and collector isolated NPN transistors can be implemented on the same chip. By comparing and analyzing the characteristics of ring oscillators and differential amplifiers constructed by both CMOS and bipolar transistors without buried layer, it was concluded that CMOS is more suitable for digital parts ,while bipolar is superior for analog parts. Concerning the bipolar input/output buffers, the patterned buried layer is required in order to improve the drivability and the high frequency response. The technology was successfully applied to a motive device, a high-speed static RAM, and improvement in access time was verified.