Shinji Onga

A simplified box (buried-oxide) isolation technology for megabit dynamic memories

A simplified version of BOX isolation technology is described. The new process has been greatly simplified over the original BOX by introducing an additional non-critical masking step. The body effect observed in narrow channel devices is reduced in the new structure. The capacitance measurement on diffused junctions in BOX structure shows smaller contributions from diode perimeter as compared to LOCOS structure. Hot electron reliability of small geometry MOSFETs has been also studied and the results are presented and discussed.

Characterization of Polycrystalline Silicon MOS Transistors and Its Film Properties. I

The characterization of polycrystalline silicon MOS transistors and its film properties are studied, with special emphasis on the relationship between crystalline defects and carrier transport phenomena. An increase in mobility with gate field in polycrystalline silicon MOS transistors and also with doping concentration in polycrystalline silicon films is observed. These phenomena are interpreted as space charge scattering effects caused by a high density of dislocations in the films. U-shaped drain current vs gate voltage curves are observed both in p-channel and n-channel polycrystalline silicon MOS transistors. The anomalous drain current in the accumulation region is interpreted as junction breakdown at the drain edge caused by crystalline imperfections in the films.

A supervised simulation system for process and device designs based on a geometrical data interface

A supervised simulation system for two-dimensional simulation has been developed covering the range from pattern layout to process simulation and also to device simulation. The system features a system controller for module programs, and the feasibility of module programs based on an intermediate topography data format with which data go between the module programs. The system controller can automatically generate appropriate jobs, assigning pertinent input data. The topography data acts as an interface through process simulation and up to device simulation. The system will eliminate laborious work for designers and greatly reduce the time required for process and device designs.

Crystallization technology for low voltage operated TFT

The authors propose a novel crystallization technology for achieving high on/off current ratio of the bottom gate TFT (thin-film transistor), especially at low operation voltage. A 6 decades on/off current ratio with 3-V gate swing was obtained utilizing this process. A 256k SRAM was fabricated using this technology. It is demonstrated that this technology improves SRAM cell margin drastically, especially at the low operation voltage.<<ETX>>

Non-equilibrium diffusion process modeling based on three-dimensional simulator and a regulated point-defect injection experiment

Presents two novel sophisticated experimental procedures for precise estimation of Si interstitial and vacancy diffusion coefficients, supported with a result from a three-dimensional process simulation system. One is impurity profile monitoring under well-controlled injected flux of point defects in three dimensional space, while the other one is in-situ TEM (transmission electron microscope) observation of the regrowth region damaged with Si ion-implantation. The authors also present a proposal for nonequilibrium Si self-diffusion process modeling based on these results. Application of the model to the ULSI process design phase is discussed.<<ETX>>

Resistivity Reduction of Polycrystalline Silicon Film by Laser Annealing

Utilizing a laser annealing technology, a drastic reduction in polysilicon sheet resistivity has been observed. The technology was successfully applied in MOS fabrication process steps, and practically no degradation in device characteristics was observed. Physical mechanism of polysilicon laser annealing is also presented, through a study of crystalline structure, mobility and carrier concentration, and the thermal instability during the subsequent thermal annealing.

A Composite Two-Dimensional Process/Device Simulation System (TOPMODE) and its Application for Total Process Designing in Submicron VLSI MOS Device Phase

A new composite two-dimensional process/two-dimensional device simulation system (TOPMODE) (FOOTNOTE: Standing for TOshiba Simulation Program for MOS DEvice.) has been developed to provide a straightforward means of predicting small-geometry device characteristics using the fabrication process sequence. Using TOP-MODE, an analysis of the anomalous subthreshold drain current peculiar to buried oxide isolation (BOX) structure device has been conducted and the physical mechanism is attributed to the impurity profile and other geometry effects. Input to TOPMODE is specially designed using key words language as a user-oriented CAD tool. Plotting functions for multidimensional perspective drawing of output results have also been installed to provide a better visual aid.

Device performance analysis using Monte-Carlo simulator for SOI MOS transistors on solid-phase-recrystallized silicon films

A Monte Carlo simulator has been developed that can trace random nucleation and regrowth characteristics for silicon-on-insulator MOS transistors and can predict the distribution of device characteristics. Activation energies for nucleation and regrowth in solid-phase were derived to be 3.9 eV and 2.8 eV, respectively. Localized states caused by the regrowth boundary were observed as a function of regrown grain size where values were two orders of magnitude larger than for bulk MOS. Threshold voltage shift and carrier mobility could be interpreted mainly in terms of the density-of-states and boundary structure; the distribution of threshold voltage and mobility were predicted closely by the Monte Carlo simulator

A Study of Nucleation and Grain Growth in Silicon Implanted a-Silicon Films

The solid-phase-recrystallization process was investigated for Si ;lmplanted amorphous silicon fiLns. This process consists of nucleation and grain growth. The recrystallization process had two stages. The nucleation of grains was dominant at the firsE stage. Both nucleati-on and grain growth occurred at the second stage. The activation energies for nucleation and grain growth were determined by a new.statistical approach, using the number of grains and the distribution of grain size. The obtained activation eneigies for nucleation and grain growth were 5.9 eV and 2.8 eV, respectively. The rate-determining step of the grain growth seemed to be similar to that of lateral solid phase epitaxy. B-2-3

The effect of thermal annealing on the grain size and electrical characteristics of arsenic ion‐implanted and laser‐irradiated polycrystalline silicon films

Q‐switched Nd: YAG laser irradiation and subsequent thermal annealing are carried out for arsenic ion‐implanted polycrystalline silicon films. Crystallographical and electrical characteristics of polycrystalline silicon are studied by using transmission electron microscopy and Hall measurements. Almost all implanted arsenic ions are electrically activated on laser irradiation, but grain growth and crystalline recovery are not found. The crystalline recovery begins to occur and carrier mobility increases during subsequent thermal annealing at temperatures of 500 °C and higher. The carrier concentration decreases due to the inactivation of the arsenic atoms with subsequent thermal annealing in the temperature range between 500 and 750 °C. At temperatures above 750 °C, grain growth and defect annihilation take place, and the carrier concentration per cm2 increases due to the diffusion and reactivation of arsenic atoms.