Shojiro Asai

A numerical model of avalanche breakdown in MOSFET's

An accurate numerical model of avalanche breakdown in MOSFETs is presented. Features of this model are a) use of an accurate electric-field distribution calculated by a two-dimensional numerical analysis, b) introduction of multiplication factors for a high-field path and the channel current path, and c) incorporation of the feedback effect of the excess substrate current induced by impact ionization into the two-dimensional calculation. This model is applied to normal breakdown observed in p-MOSFETs and to negative-resistance breakdown (snap-back or switchback breakdown) observed in short-channel n-MOSFETs. Excess substrate current generated from channel current by impact ionization causes a significant voltage drop across the substrate resistance in short-channel n-MOSFETs. This voltage forward-biases the source-substrate junction and increases channel current causing a positive feedback effect. This results in a decrease of the breakdown voltage and leads to negative-resistance characteristics. Current-voltage characteristics calculated by the present model agree very well with experimental results. Another model, highly simplified and convenient for device design, is also presented. It predicts some advantages of p-MOSFETs over n-MOSFETs from the standpoint of avalanche breakdown voltage, particularly in the submicrometer channel-length range.

Submicrometer MOSFET structure for minimizing hot-carrier generation

This paper reports on investigation of channel hot-carrier generation for various device structures. The dependences of channel hot-carrier generation on MOSFET structure are characterized by measuring the gate current and the substrate current as low as on the order of 10-15A. The measured gate current due to hot-electron injection into the oxide is modeled numerically as thermionic emission from heated electron gas over the Si-SiO 2 energy barrier. The substrate current due to hot-hole injection into the substrate is also modeled analytically. On the basis of the experiments and analyses, two device structures are proposed for minimizing hot-carrier generation and associated problems in submicrometer MOSFET: a graded drain junction structure and an offset gate structure. The proposed device structures provide remarkable improvements, raising by 2 V the highest applicable voltages as limited by hot-electron injection, as well as raising by 1-3 V the drain sustaining voltages as determined by the substrate hot-hole current. The influence of electron-beam radiation on the gate oxide is also discussed in relation to the trapping of hot electrons.

Technology challenges for integration near and below 0.1 /spl mu/m

Technology challenges for silicon integrated circuits with a design rule of 0.1 /spl mu/m and below are addressed. We begin by reviewing the state-of-the-art CMOS technology at 0.25 /spl mu/m currently in development, covering a logic-oriented processes and dynamic random access memory (DRAM) processes. CMOS transistor structures are compared by introducing a figure of merit. We then examine scaling guidelines for 0.1 /spl mu/m which has started to deviate for optimized performance from the classical theory of constant-field scaling. This highlights the problem of nontrivial subthreshold current associated with the scaled-down CMOS with low threshold voltages. Interconnect issues are then considered to assess the performance of microprocessors in 0.1 /spl mu/m technology. 0.1 /spl mu/m technology will enable a microprocessor which runs at 1000 MHz with 500 million transistors. Challenges below 0.1 /spl mu/m are then addressed. New transistor and circuit possibilities such as silicon on insulator (SOI), dynamic-threshold (DT) MOSFET, and back-gate input MOS (BMOS) are discussed. Two problems below 0.1 /spl mu/m are highlighted. They are threshold voltage control and pattern printing. It is pointed out that the threshold voltage variations due to doping fluctuations is a limiting factor for scaling CMOS transistors for high performance. The problem with lithography below 0.1 /spl mu/m is the low throughput for a single probe. The use of massively parallel scanning probe assemblies working over the entire wafer is suggested to overcome the problem of low throughput.

Two-dimensional numerical analysis of stability criteria of GaAs FET's

Stability criteria of GaAs junction-gate FETs are studied by two-dimensional numerical analysis. The analysis covers the wide range of device geometry from the state of the art FET to the so-called Gunn effect digital devices. It is found that a GaAs FET exhibits either of the following three types of characteristics depending upon device geometry and doping concentration. First, for a thin channel with high doping concentration, the device tends to behave as a normal junction-gate FET with saturating current-voltage characteristics. This is even true when the n-l (device length) and n.d (device thickness) products exceed the previously accepted criteria for Gunn oscillation. Second, a stable negative resistance (SNR) is observed in devices with a moderate channel thickness. Third, for a thick channel, the device exhibits a Gunn oscillation with the domain propagating from the gate edge to the drain. These three categories of behavior are mapped on the nd plane with the help of simple analytic considerations. The map is found to compare well with experimental results.

An As-P(n + -n - )double diffused drain MOSFET for VLSI's

An As-P(n+-n-) double diffused drain is characterized as one of the most feasible device structures for VLSIs from the overall viewpoint of device design. This device makes good use of both As, suitable for microfabrication, and P, in realizing a graded junction. The feasibility of this double diffused drain is investigated comparing it with a conventional As drain over the wide range of effective channel length from 0.5 to 5 µm. We have also succeeded in directly measuring hot-hole gate current as low as on the order of 10-15A. This current seems to have an important influence on the hot-carrier effects. On the basis of the experiments and simulations using the two-dimensional process/device analysis programs SUPREM and CADDET, it is shown that this device structure provides remarkable improvements, not only in terms of channel hot-electron effects, but also avalanche hot-carrier effects, which are more responsible for hot-carrier related device degradation due to impact ionization at the drain. In addition, this structure has almost the same short channel effect characteristics, for example threshold-voltage lowering as a conventional MOSFET.

Analytical models of threshold voltage and breakdown voltage of short-channel MOSFETs derived from two-dimensional analysis

An approximate analytical solution for the surface potential is used to derive the threshold voltage. It is shown that the surface potential depends exponentially on the distance from the drain, and this causes the threshold voltage to decrease exponentially with decreasing channel length. The analytical dependence of threshold voltage on device dimensions, doping, and operating conditions is verified by accurate two-dimensional calculations, and the accuracy of the model is attained by slight modification. The breakdown voltage of a short-channel n-MOSFET is lowered by a positive feedback effect of excess substrate current. From two-dimensional analysis of this mechanism, a simple expression of the breakdown voltage is derived. Using this model, the scaling down of MOSFETs is discussed. The simple models of threshold and breakdown voltage of short-channel MOSFETs are helpful both for circuit-oriented analysis and process diagnosis where statistical use of the model is often needed.

A soft error rate model for MOS dynamic RAM's

A soft error rate analysis model for MOS dynamic RAMs is presented. The soft error rate can be quantitatively calculated by using a solution of the equations for diffusion and collection of alpha-particle-induced excess electrons and by combining a statistical treatment of alpha particle energy, incidence angles, and incidence positions with the noise charge calculation. The model is then applied to analyze a soft error experiment on 64-kbit dynamic RAMs. It is shown that soft error characteristics with regard to signal charge (critical charge), as well as alpha energy and incidence angle dependencies, can be definitely determined. The model can also be used to predict the location of soft errors in MOS dynamic RAMs.

GaAs dual-gate Schottky-barrier FET's for microwave frequencies

The benefits inherent in the tetrode structure and the potential of GaAs are combined to realized a dual-gate FET with low noise and a wide dynamic range at microwave frequencies. A design theory of the dual-gate FET is constructed on the basis of the Lehovec-Zuleeg model for single-gate FETs. The theory has led to a new device structure having a second gate with a deeper pinchoff voltage than the first which shows improved gain and noise performance. Also derived is the importance of minimizing parasitic feedthrough due, for example, to packages. Samples were fabricated using n-type epitaxial GaAs. The first and second gates were Schottky barriers, 1.2 and 2.5 µm long. The improved channel structure was accomplished by reducing the thickness of the epitaxial layer under the first gate. Samples were mounted and characterized in specially designed small-size ceramic packages with a feedthrough capacitance of only 0.004 pF. The possibility of gain control by means of second gate bias over a wide bandwidth is demonstrated.

New grooved-gate MOSFET with drain separated from channel implanted region (DSC)

A new grooved-gate MOSFET with its drain separated from channel implanted regions (DSC structure) is proposed for the purpose of obtaining higher breakdown voltages: drain sustaining voltage and highest applicable voltage placed by hot-carrier effects. Nonimplanted regions between channel implanted and source/drain regions are a unique feature of this device structure. The self-aligned nonimplanted region in the channel is obtained by using silicon dioxide and resist overhangs. These overhangs are fabricated by grooving the silicon substrate. The DSC structure helps reduce the electric field at the drain. Characteristics of experimental devices are presented and compared with those of conventional MOSFETs, from the viewpoint of overall VLSI device design. This device structure is shown to provide remarkable improvements, achieving a 3- or 4-V increase in drain sustaining voltage, as well as a 1- or 2-V increase in the highest applicable voltage as limited by hot-electron injection. In addition, the proposed device can alleviate such short-channel effects as Vthlowering, and in particular, diminish narrow-channel effects. The influence of nonimplanted length on breakdown voltage is also clarified using the CADDET, two-dimensional analysis program.

Excess gate current analysis of junction gate FET's by two- dimensional computer simulation

Gate current in a JFET under high drain bias is much higher than expected from the classical theory for reverse-biased p-n junctions. This excess gate current is caused by minority carriers generated by low-level impact ionization in the conducting channel, while the so-called breakdown voltage is determined by high-level avalanche multiplication near the gate edge at the surface. A simple one-dimensional model for the excess gate current is proposed. This model is based on the results of two-dimensional numerical analysis, which neglects the minority carrier motion. The excess gate current and avalanche breakdown voltage are calculated from one-dimensional ionization integrals, which are obtained numerically by utilizing the solution of two-dimensional analysis. The reverberant effect of the generated carriers on the potential distribution is assumed to be negligible. The results of the calculation are in good agreement with experimental results, without any adjustable parameters. Moreover, various impurity doping profiles are analyzed for the purpose of minimizing excess gate current. The present model requires a reasonably short computation time and is useful for designing JFET devices.