Masahiro Ushiyama

Read-disturb degradation mechanism due to electron trapping in the tunnel oxide for low-voltage flash memories

This paper describes the degradation of read-disturb characteristics related to time-dependent current caused by electron trapping in tunnel-oxide film. The time-dependent current, rather than the stress-induced leakage current, affects the threshold-voltage shift in memory cells with relatively thick tunnel oxide (>7 nm) and long disturbance time. Programming and erase endurance affects read disturb such that the read-disturb lifetime is improved in memory cells with nitrided oxide which exhibit long-endurance characteristics.<<ETX>>

An 80 ns 1 Mb flash memory with on-chip erase/erase-verify controller

An internal erase and erase-verify control system implemented in all electrically erasable, reprogrammable, 80-ns, 1-Mb flash memory suitable for in-system reprogram applications is discussed. This system features a command signal latch, a sequence controller, and a verify voltage generator. Timing in the electrical erase mode is shown. The erase mode is initiated by a 50-ns pulse. An erase and erase-verify sequence is automatically conducted in a chip without any further external control. The internal status can be checked through a status-polling mode. The 80-ns access time results from advanced sense amplifiers, as well as from low-resistance polysilicide word lines and scaled periphery transistors. For sensitivity and speed of the sense circuits, a pMOSFET with gate connected to drain is used as a load transistor. Compared with a conventional sense amplifier with a grounded-gate pMOSFET load, the shorter channel length of the pMOSFET used here gives the same sensitivity, reducing the stray capacitance problem. Together with a signal voltage swing reduced by a threshold voltage of the pMOSFET, this is essential for access speed. Simulation shows a 30-ns reduction of access time at a V/sub cc/ of 4.25 V. Schmoo plots of the address access time indicate that V/sub cc min/ is 3.4 V, demonstrating the proper operation of the automatic erase scheme.<<ETX>>

Two dimensionally inhomogeneous structure at gate electrode/gate insulator interface causing Fowler-Nordheim current deviation in nonvolatile memory

The gate electrode polycrystalline silicon (gate poly-Si)/gate insulator SiO/sub 2/ interface structure has been studied for obtaining reliable nonvolatile memory devices. The voltage deviation of Fowler-Nordheim tunneling current of the devices is discussed in terms of the SiO/sub 2/ surface roughness. High resolution scanning electron microscope (SEM) and atomic force microscope (AFM) measurements indicate that two dimensional nanometric oxide ridges are formed at the interface. It was found that a phosphorus dose below 2*10/sup 15/ cm/sup -2/, an annealing temperature below 900 degrees C, and the use of arsenic as a dopant resulted in the smooth SiO/sub 2/ surfaces. The reduction in the voltage deviation of the tunneling current is correspondingly obtained under these conditions. The oxide ridge growth can be explained by excess phosphorus distribution at grain boundaries and phosphorus-rich SiO/sub 2/ formation.<<ETX>>

Nanometer Structure of Gate Electrode/Gate Insulator Interface and Anomalous Voltage Deviation of Tunneling Current in Submicron MOS Devices

Gate polycrystalline silicon/gate insulator interface characteristics is shown to be correlated to Fowler-Nordheim tunneling current flowing through a gate insulator film. When the tunneling area of the current is less than I p-2, there appears an anomalous voltage deviation of the tunneling current. It is also determined that low-temperature processing, a low-phosphorous density for the gate polycrystalline silicon, and a two-layer gate insulator film consisting of Si3Na/SiO2 are effective for reducing the deviation.

Improving program/erase endurance by controlling the inter-poly process in flash memory

Using poly-Si gate MOS capacitors, the tunnel oxide degradation due to high electric field stress is shown to be accelerated by the oxidation of the Si/sub 3/N/sub 4/ film in inter-poly ONO films and by high-temperature annealing. Microscopic Raman spectroscopy confirms that increased tensile stress in poly-Si gates leads to tunnel oxide degradation, Therefore, using CVD-SiO/sub 2/ film as the top oxide in inter-poly ONO films or using only a CVD-SiO/sub 2/ film as the inter-poly film, and reducing the high-temperature annealing time after poly-Si gate formation, will significantly increase the program/erase endurance of flash memory.

Highly Reliable N2O-Oxynitrided Tunnel Oxides for Flash Memory

Cycling of up to lff is conhrmed in a flash memory cell with Np-oxynitrided SiQ as a tunnel oxide. This improvement is shown to be realized by annealing a SiO2 film in Np ambient in a conventional furnace. XANES (X-ray AbsorptionNearEdgeStructurQ analysis clarifies thatthe higher resistance of an oxynitrided SiO, film to high electric-field stress is due to *re presence of fewer unstable Si O bonds than in conventional SiO, film.

Sub-10-ps gate delay by reducing the current crowding effect at an extension

In short-channel CMOS devices with extension structures, current crowding was found to occur in the source extension, significantly degrading current drivability. Reducing this effect by using high-dose extensions and low parasitic capacitance provided by a localized punchthrough stopper layer produced high drivability, enabling a sub-10-ps CMOS gate delay to be attained.