Ho-young Song

An 80 nm 4 Gb/s/pin 32 bit 512 Mb GDDR4 Graphics DRAM With Low Power and Low Noise Data Bus Inversion

4 Gb/s/pin 32 bit 512 Mb GDDR4 (Graphics Double Data Rate 4) SDRAM was implemented by using an 80 nm CMOS process. It employs a data bus inversion (DBI) coding to overcome the bottleneck of a parallel single-ended signaling, a power consumption of I/O, power supply noise, and crosstalk. Both DBI AC and DC modes are combined to a single circuit by eliminating the feedback path of a conventional DBI AC circuit while achieving high-speed operation. The proposed DBI circuit uses an analog majority voter insensitive to mismatch for small area and delay. Ronmiddot tuning further improves the voltage and time margin by adding a user-supplied offset to auto-calibrated Ronmiddot. In addition, a dual duty cycle corrector (DCC) is used to reduce duty error and jitter by averaging two outputs of two DCCs. Measured results show that DBI DC coding reduces the peak-to-peak jitter from 65.5 ps to 44.5 ps and the voltage fluctuation from 183 mV to 115 mV at the data rate of 4 Gb/s with the 2 V.

An 80nm 4Gb/s/pin 32b 512Mb GDDR4 Graphics DRAM with Low-Power and Low-Noise Data-Bus Inversion

A 4Gb/s/pin 32b parallel 512Mb GDDR4 SDRAM is implemented in an 80nm DRAM process. It employs a data-bus inversion coding scheme with an analog majority voter insensitive to mismatch, which reduces peak-to-peak jitter by 21 ps and voltage fluctuation by 68mV. A dual duty-cycle corrector is proposed to average duty error, and tuning is added to the auto-calibration of driver and termination impedance.

Digitally-controlled DLL and I/O circuits for 500 Mb/s/pin /spl times/16 DDR SDRAM

DLL and improved I/O circuits are for 500 Mb/s/pin DDR SDRAM. This digitally-controlled DLL has inherent duty cycle correction capability, enabling fast re-locking upon standby-mode exit. Data input circuits, such as internal delay control and digital sense amplifier, reduce setup/hold window to 0.3 ns. The output data driver has 62% decreased pattern-dependent skew.