Hong-ki Kim

Improvement of crosstalk on 5M CMOS image sensor with 1.7x1.7μm2 pixels

Crosstalk of CMOS Image Sensor (CIS) causes degradation of spatial resolution, color mixing and leads to image noise. Crosstalk consists of spectral, optical and electrical components, but definition of each component is obscure and difficult to quantify. For the first time, quantifiable definition of each component is proposed to perform crosstalk analysis in this paper. Contribution of each component to the total crosstalk is analyzed using opto-electrical simulation. Simulation is performed with an internally developed 2D finite difference time domain (FDTD) simulator coupled to a commercial device simulator. Simulation domain consists of set of four pixels. Plane wave propagation from micro-lens to the photodiode is analyzed with FDTD and the optical simulation result is transformed into the photo-current in the photodiode using electrical simulation. The total crosstalk consists of 43% of spectral crosstalk, 14% of optical cross talk, and 43% of electrical crosstalk at the normal incident light. Spectral crosstalk can be suppressed through careful selection of color filter materials with good selectivity of color spectrum. Characteristics of crosstalk and photosensitivity show contrary trend to one another as a function of color filter thickness. Therefore, the crosstalk target is fixed and simulation is performed to determine the minimum color filter thickness that satisfies the crosstalk target. By color filter material and thickness optimization, 10% increase in photosensitivity and 7% decrease spectral crosstalk were obtained. Electrical crosstalk showed 11% and 9% improvement through applying to new implantation process and stacking multi-epi layer on the p-type substrate, respectively.

High performance pMOSFET with BF/sub 3/ plasma doped gate/source/drain and S/D extension

A BF/sub 3/ Plasma doping (PLAD) process has been utilized in source/drain/gate and shallow S/D extension for high performance 0.18 /spl mu/m pMOSFET. Gate oxide reliability, drain current, and transconductance of the pMOSFET with BF/sub 3/ PLAD are remarkably improved compared to those of BF/sub 2/ ion implanted devices. Cobalt salicide formation is also compatible with the plasma doped S/D junction.

7.1 A 1/4-inch 8Mpixel CMOS image sensor with 3D backside-illuminated 1.12μm pixel with front-side deep-trench isolation and vertical transfer gate

According to the trend towards high-resolution CMOS image sensors, pixel sizes are continuously shrinking, towards and below 1.0μm, and sizes are now reaching a technological limit to meet required SNR performance [1-2]. SNR at low-light conditions, which is a key performance metric, is determined by the sensitivity and crosstalk in pixels. To improve sensitivity, pixel technology has migrated from frontside illumination (FSI) to backside illumiation (BSI) as pixel size shrinks down. In BSI technology, it is very difficult to further increase the sensitivity in a pixel of near-1.0μm size because there are no structural obstacles for incident light from micro-lens to photodiode. Therefore the only way to improve low-light SNR is to reduce crosstalk, which makes the non-diagonal elements of the color-correction matrix (CCM) close to zero and thus reduces color noise [3]. The best way to improve crosstalk is to introduce a complete physical isolation between neighboring pixels, e.g., using deep-trench isolation (DTI). So far, a few attempts using DTI have been made to suppress silicon crosstalk. A backside DTI in as small as 1.12μm-pixel, which is formed in the BSI process, is reported in [4], but it is just an intermediate step in the DTI-related technology because it cannot completely prevent silicon crosstalk, especially for long wavelengths of light. On the other hand, front-side DTIs for FSI pixels [5] and BSI pixels [6] are reported. In [5], however, DTI is present not only along the periphery of each pixel, but also invades into the pixel so that it is inefficient in terms of gathering incident light and providing sufficient amount of photodiode area. In [6], the pixel size is as large as 2.0μm and it is hard to scale down with this technology for near 1.0μm pitch because DTI width imposes a critical limit on the sufficient amount of photodiode area for full-well capacity. Thus, a new technological advance is necessary to realize the ideal front DTI in a small size pixel near 1.0μm.

Inhibitory Effect of the Selected Heavy Metals on the Growth of the Phosphorus Accumulating Microorganism, Acinetobacter sp.

This study was initiated to evaluate the inhibitory effect of selected heavy metals on the growth of Acinetobacter sp. Down as one of the phosphorus accumulating microorganisms (PAO) involved in the enhanced biological phosphorus removal (EBPR) process of the wastewater treatment plant. Acinetobacter sp. was initially selected as a starting model microorganism and was grown under aerobic condition for this experiment. The heavy metals selected and investigated in this study were cadmium (Cd), copper (Cu), mercury (Hg), nickel (Ni), and zinc (Zn). Median and threshold inhibitory concentrations for Cd, Cu, Hg, Ni, and Zn were 2.95 and 1.45, 4.92 and 2.53, 0.03 and 0.02, 1.12 and 0.43, 14.84 and 5.46 mg , respectively. We demonstrated that most of heavy metals tested in the experiment inhibited the growth of Acinetobacter sp. in the range of predetermined concentrations. Based on the data obtained from the experiment, Hg was the most sensitive to Acinetobacter sp., then Ni, Cd, Cu, and Zn in order.

The features and characteristics of 5M CMOS image sensor with 1.9/spl times/1.9/spl mu/m/sup 2/ pixels

5 mega CMOS image sensor with 1.9mum-pitch pixels has been implemented with 0.13 mum low power CMOS process. By applying 4-shared pixel architecture, 2.5V operation voltage, and tight design rules for some critical layers in pixels, high fill factor and the corresponding high saturation could be obtained. Image lag was sufficiently suppressed by pulse-boosting of transfer gate voltage and electrical cross-talk was suppressed by use of n-type epitaxial layer. It is shown that several sophisticated processes improve sensitivity, temporal random noise, and dark current. With this technology, full 5-mega density CMOS image sensor chips have been successfully developed

Novel plasma enhanced atomic layer deposition technology for high-k capacitor with EOT of 8 /spl Aring/ on conventional metal electrode

We have developed a plasma enhanced atomic layer deposition(PEALD) technology for high-k dielectrics such as Al/sub 2/O/sub 3/,Ta/sub 2/O/sub 5/ and HfO/sub 2/. Film quality and throughput of PEALD are far superior to that of ALD which has been spotlighted as a deposition technology for next generation semiconductor devices. We have obtained a extremely low equivalent oxide thickness(EOT) of 8 /spl Aring/ from HfO/sub 2/ film, which has not been reported in conventional metal-based memory capacitors up to now. It was confirmed that PEALD-Al/sub 2/O/sub 3/ and Ta/sub 2/O/sub 5/ films are superior to those using any other deposition techniques and very useful as System-on-Chip(SoC) capacitors.