Jen-Chieh Liu

Built-in Jitter Measurement Circuit With Calibration Techniques for a 3-GHz Clock Generator

This paper proposes a 3-GHz built-in jitter measurement (BIJM) circuit to measure clock jitter on high-speed transceivers and system-on-chip (SoC) systems. The proposed BIJM circuit adopts a high timing resolution and self-calibration techniques. To eliminate process variation effects in 3 GHz systems, this study proposes an auto-calibration technique for the self-refereed circuit and other calibration techniques for the time amplifier (TA) and vernier ring oscillator (VRO), respectively. These calibration techniques can reduce the timing resolution variation of the vernier ring oscillator and the gain variation of the TA by 66% and 65%, respectively. This reduces the timing resolution variation of BIJM by 60%. Because the vernier ring oscillator and time amplifier achieve a small timing resolution, the BIJM circuit does not need an additional jitter-free reference signal using the self-refereed circuit. This study fabricated the BIJM circuit using the UMC 90-nm CMOS process. The BIJM circuit has a power consumption measuring 11.4 mW, and its core area is 120 μm × 320 μm. The BIJM circuit measured the Gaussian distribution jitter at a 1.8 ps timing resolution with a 3-GHz input clock frequency.

A 0.6-V 800-MHz All-Digital Phase-Locked Loop With a Digital Supply Regulator

This paper proposes an ultra-low-voltage all-digital phase-locked loop (ADPLL) with a digital supply regulator (DSR). The DSR maintains an RMS jitter for a 280-MHz output signal of less than 0.55% when a 100-kHz to 100-MHz supply noise is produced on a digitally controlled oscillator (DCO). The DCO uses the two-step timing resolution of a digitally controlled varactor to achieve the high timing resolution. The proposed digital loop filter can reduce the area cost and critical path using the double-edge trigger technique. For a low supply voltage, the DCO and the time-to-digital converter use bulk-controlled techniques to increase the highest operating frequency and timing resolution, respectively. When the ADPLL output is 800 MHz at 0.6 V, the power consumption and core area are 656 μW and 0.02 mm2, respectively, in a 90-nm CMOS process.

A High Precision Fast Locking Arbitrary Duty Cycle Clock Synchronization Circuit

This study proposes a high precision fast locking arbitrary duty cycle clock synchronization (HPCS) circuit. This HPCS is capable of synchronizing the external clock and the internal clock in three clock cycles. By using three innovative techniques, the proposed HPCS can also reduce the clock skew between the external clock and the internal clock in a chip. First, by modifying the mirror control circuit, the HPCS operates correctly with an arbitrary duty cycle (25%-75%) clock signal. Second, the HPCS works precisely and ignores the effect of output load changes by moving the measurement delay line beyond the output driver. Finally, the HPCS can enhance the resolution between the external clock and internal clock with a fine tuning structure. After phase locking, the maximum static phase error is less than 20 ps. The proposed chip is fabricated in a TSMC 130-nm CMOS process, and has an operating frequency range from 300 to 600 MHz. At 600 MHz, the power consumption and rms jitter are 2.4 mW and 3.06 ps, respectively. The active area of this chip is 0.3 × 0.13 mm2.

A 0.9- to 8-GHz VCO With a Differential Active Inductor for Multistandard Wireline SerDes

This study demonstrates a wide frequency tuning range LC voltage-controlled oscillator (LC-VCO) with an active inductor in a 90-nm CMOS process. As the proposed LC-VCO is intended to be extremely flexible without redesign for several new-generation SerDes interfaces, a wide operating frequency makes the phase-locked loop (PLL) applicable to the multistandards. To demonstrate a highly competitive design, a quality (Q) factor enhancement technique has been also demonstrated to reduce the loss from the active inductor, leading to an appropriate phase noise over the entire tuning range. At a supply of 1.2 V, the fabricated LC-VCO provides a frequency tuning range of 0.9-8 GHz (160%) with power consumption of 3.2-19.1 mW. The measured phase noise is from -105 to -118 dBc/Hz at a 1-MHz offset. Realized in a fully integrated PLL chip, it occupies an active area of 0.08 × 0.16 mm2.

A time-to-digital converter using multi-phase-sampling and time amplifier for all digital phase-locked loop

This work presents a high timing resolution and wide measured timing range time-to-digital converter (TDC) for all digital phase-locked loop (ADPLL). The multi-phase outputs of digital controlled oscillator (DCO) utilize to sample the timing difference and extend its detectable timing range. A time amplifier (TA) is further applied to enhance the timing resolution. This design requires less silicon area compared to traditional TDCs. The TDC is realized by using a 90 nm CMOS process. TDC achieves a 6.8 ps timing resolution and a measured timing range from 12 ps to 9.5 ns. The DNL and INL are ±0.85 LSB and ±3.5 LSB, respectively. The power dissipation is 240 uW at 0.5 V supply voltage.

All-Digital PLL Using Pulse-Based DCO

A 150-450-MHz, all-digital phase locked-loop (ADPLL) in a 0.1 um CMOS process is presented. The pulse- based digitally controlled oscillator (PB-DCO) performs a high resolution and wide range. The bulk-controlled varactor minimizes jitter performance. The worst case for frequency acquisition is 32 reference clock cycles. The multiplication factor is 2-63. The rms and peak-to-peak jitters are 6.7 ps and 44 ps at 450-MHz, respectively. Power consumption is 16.2 mW at 450-MHz.

A 6-GHz Built-in Jitter Measurement Circuit Using Multiphase Sampler

This brief presents a 6-GHz built-in jitter measurement (BIJM) with the time amplifier (TA) and the multiphase sampler (MPS) to achieve a 1-ps timing resolution. The proposed MPS can reduce the area, and the TA can extend the total timing resolution of BIJM. The self-referenced circuit with the autocalibration technique can eliminate the process variations and create a reference clock being a sampled signal. Using the calibration technique, the gain variation of TA and the timing resolution variation of MPS can be aligned to achieve a 1-ps timing resolution. The sense amplifier delay flip-flop uses the bulk input to reduce the measured error. The BIJM is fabricated by a 90-nm CMOS process. The core area of BIJM is 130 μm × 200 μm, and the power consumption is 20.4 mW with the I/O buffers.

A 0.3-V all digital crystal-less clock generator for energy harvester applications

A 0.3 V all digital crystal-less clock generator (CLCG) is presented for a hearing aid application. The all digital CLCG uses frequency difference between the ring oscillator and the digital controlled oscillator (DCO) to create a mapping table under process and temperature variations. The digital loop filter (DLF) adopts a successive-approximation register (SAR) algorithm for fast locking time. Thus, the worse case of locking time is 73 output cycles. For a hearing aid application, the core area of CLCG and hearing aid system are 62 × 78 μm2 and 1900 × 1920 μm2, respectively, in 65 nm CMOS process. The frequency accuracy is 12 MHz ±3.5% in four test chips. The power consumption is 5 μW. In the period jitter, the RMS and peak-to-peak jitters are 326.4 ps and 2.05 ns, respectively. The frequency drift is smaller than ±4.3% from 0 to 100°C. Thus, this work is also used for energy harvester applications.

A loading effect insensitive and high precision clock synchronization circuit

This study proposes a output loading effect insensitive and high precision clock synchronization (HPCS) circuit which can accept variable duty cycle clock signal. This HPCS is capable of synchronizing the external clock and the internal clock in 3 clock cycles. By using three innovative techniques, the proposed HPCS can also reduce the clock skew between the external clock and the internal clock in a chip. First, by modifying the mirror control circuit, the HPCS operates correctly with an arbitrary duty cycle (25% ~ 75%) clock signal. Second, the HPCS works precisely and ignores the effect of output load changes by moving the measurement delay line beyond the output driver. Finally, the HPCS can enhance the resolution between the external clock and internal clock with a fine tuning structure. After phase locking, the maximum static phase error is less than 20 ps. The proposed chip is fabricated in a TSMC 130 nm CMOS process, and has an operating frequency range from 300 MHz to 600 MHz. At 600 MHz, the power consumption and rms jitter are 2.4 mW and 3.06 ps, respectively. The active area of this chip is 0.3×0.13 mm2.

A chaotically injected timing technique for ring-based oscillators

This work proposes a chaotically injected timing technique (CITT) for ring-based oscillators. The quality of clock signal affects the normal motion of the entire circuit. In many oscillators and clock generators show the performance comparison through jitters and phase noise. The injection-locked ring-based oscillators have advantages of jitters, phase noise and area cost. However, there is a contingent effect, injected spur. By adopting the CITT, the injected phase pattern can be randomized and break the periodicity of injected signal to solve the high injected spur effect. The CITT can reduce the level of phase noise by 29 dB compared to the free-run oscillator. The experiment chip of the proposed CITT is implemented by 90 nm CMOS process. The measured output frequency is 5 GHz at supply voltage of 1 V. The level of phase noise is -99 dBc at frequency offset of 1 MHz under injected frequency of 1 GHz.