Hongjin Kim

A Design of a Wireless Power Receiving Unit With a High-Efficiency 6.78-MHz Active Rectifier Using Shared DLLs for Magnetic-Resonant A4 WP Applications

This paper presents a full-CMOS wireless power receiving unit (WPRU) with a high-efficiency 6.78-MHz active rectifier and a dc-dc converter for magnetic-resonant alliance for wireless power (A4WP) applications. The proposed high-efficiency active rectifier with delay-locked loop (DLL) is a highly efficient receiver circuit intended for use in resonant wireless charging applications with a resonant frequency of 6.78 MHz. Each MOSFET of the proposed rectifier is turned on and off based on the ac input voltage. The delay between the ac input current and the ac input voltage due to the delays of internal blocks such as voltage limiter, level shifter, gate driver, and comparator will cause the reverse leakage current, degrading the power efficiency. Thus, the proposed active rectifier adopts the DLL to compensate for the delay caused by internal blocks, which leads to the removal of reverse leakage current and the power efficiency maximization. Moreover, to maximize power efficiency, negative impedance circuit (NIC) is also adopted to minimize switching loss. In the case of dc-dc converter, phase-locked loop is adopted for the constant switching frequency in process, voltage, and temperature (PVT) variation to solve the efficiency reduction problem, especially by heat. This chip is implemented using 0.18 μm BCD technology with an active area of 3.5 mm × 3.5 mm. When the magnitude of the ac input voltage is 8.95 V, the maximum efficiencies of the proposed active rectifier and dc-dc converter are 91.5% and 92.7%, respectively. The range of ac input voltage is 3-20 V, and the efficiency of the WPRU is about 80.86%.

A Low Power, Small Area Cyclic Time-to-Digital Converter in All-Digital PLL for DVB-S2 Application

In this paper, a low power, small area cyclic time-to-digital converter in All-Digital PLL for DVBS2 application is presented. Coarse and fine TDC stages in the two-step TDC are shared to reduce the area and the current consumption maintaining the resolution since the area of the TDC is dominant in the ADPLL. It is implemented in a 0.13 ,m CMOS process with a die area of 0.12 mm². The power consumption is 2.4 mW at a 1.2 V supply voltage. Furthermore, the resolution and input frequency of the TDC are 5 ps and 25 MHz, respectively.

Wide input range, high-efficiency magnetic resonant wireless power receiver

This article presents a full-CMOS receiver for magnetic resonant wireless battery charging system. A wide-input range CMOS multi-mode active rectifier is proposed for a magnetic resonant wireless battery charging system. The configuration is automatically changed with respect to the magnitude of the input AC voltage. The output voltage of the multi-mode rectifier is sensed by a comparator. Furthermore, the configuration of the multi-mode rectifier is automatically selected by switches as original rectifier mode, one-stage voltage multiplier or two-stage voltage multiplier mode. As a result, a rectified DC output voltage is from 7.5 to 19 V for an input AC voltage of 5–20 V. This chip is implemented using 0.35 μm BCD technology with an active area of around 5 × 2.5 mm2. When the magnitude of the input AC voltage is 10 V, the power conversion efficiency of the multi-mode active rectifier is about 94%.The efficiency of the receiver is about 60% when the distance between the transmitter and receiver is about 1 m.

An Ultra-Low-Power Super Regeneration Oscillator-Based Transceiver With 177-

An ultra-low-power super regeneration oscillator (SRO) transceiver with a 177- μW ultra-low-power phase-locked loop (PLL) and automatic quench waveform generator (QWG) is presented. In order to decrease the PLL power consumption, the leakage current is measured at the VCO control voltage node, and the control voltage is compensated by the digital part. As a result, the frequency can be maintained near 2.37 GHz after the PLL is turned off. An automatic QWG circuit that can search for the critical current of the SRO automatically is proposed in order to mitigate the process, voltage, temperature variations of the conventional QWG. This chip is implemented using 90-nm CMOS technology. The die area of the full transceiver is 3 mm × 4 mm and that of the PLL is 0.4 mm × 0.9 mm. The leakage compensation and high-Q voltage-controlled oscillator (VCO) approach results in a frequency offset of 70 kHz and fluctuation of ±75 kHz (the maximum frequency error is 145 kHz at 60 ppm). The phase noise of the VCO output at 2.37 GHz is -103.5 dBc/Hz at 1-MHz offset. The average power consumption of the PLL is 177 μW from a 1.2-V supply voltage.

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This paper presents a small area LC VCO with an on-chip 3-D solenoid inductor using the 0.13 m digital CMOS process. The on-chip solenoid inductor is vertically constructed by using Metal and Via layers with a horizontal scalability. Compared to a spiral inductor, it has the advantage of occupying a small area and this is due to its 3-D structure. The LC VCO with solenoid inductor is fabricated in 0.13 m process and the die area of solenoid inductor is 0.013 mm2. The measured phase noise is -110.61 dBc/Hz at 1MHz offset when the output frequency is 5.195 GHz. The measured tuning range is about 1.1 GHz. The power consumed from 1.2 V supply, is 13.2 mW.

W Leakage-Compensated PLL and Automatic Quench Waveform Generator

This paper presents a multi-channel capacitive touch sensing unit for SoC applications. This unit includes a simple common processing unit and switch array to detect the touch sensing input by capacitive-time(C-T) conversion method. This touch sensor ASIC is designed based on the Capacitive-Time(C-T) conversion method to have advantages of small current and chip area, and the minimum resolution of the unit is 41 fF per count with the built-in sensing oscillator, LDO regulator and I2C for no additional external components. This unit is implemented in 0.18 um CMOS process with dual supply voltage of 1.8 V and 3.3 V. The total power consumption of the unit is 60 uA and the area is 0.26 mm2.

A 4.1–5.2 GHz LC VCO using a vertical solenoid inductor in 0.13 μm digital CMOS

In this paper we have presented a single inductor single output dc-dc synchronous boost converter using 5MHz switching frequency, ultimately reducing the inductor and capacitor sizes. Synchronous rectification has been employed. In the feedback loop we proposed a technique of smooth loop handover. For the dynamic load conditions we propose another technique to reduce ripples at higher loads. Control logic and buffer blocks are designed to generate proper signals to drive power MOSFETs. Input supply is 1.8V, switching frequency is 5MHz and output is 3.7V.

Low power multi-channel capacitive touch sensing unit using capacitor to time conversion method

This paper presents an inductive coupling wireless power receiver with high efficiency active rectifier and multi feedback LDO regulator. The synchronous active rectifier with the zero current sensing is proposed to achieve the high efficiency minimizing the reverse leakage current. Multi Feedback LDO regulator is proposed to implement the output voltage regulation, over voltage protection, over current limit, and adaptive communication limit sharing the single power transistor. This chip is implemented using 0.18 μm BCD technology with an active area of 4.0 mm × 4.0 mm. The maximum power conversion efficiency of the Active Rectifier is 94.2 % when the load current is 800 mA.

3.7V high frequency DC-DC synchronous boost converter with smooth loop handover

This paper presents a low power FSK transceiver with ADPLL based on direct modulation and integrated SPDT switch for Bluetooth low energy application. To ensure that the proposed low power transceiver can operate at 1 Mbps data rate, FSK modulation is implemented using an all-digital phase locked-loop with direct modulation technique. The SPDT switch is integrated to share the antenna and matching network between the transmitter and receiver, thus minimizing the system cost by reducing external components. The transceiver is implemented using 1P6M 55-nm CMOS technology. The die area of the transceiver with DC-DC converter is 1.79 mm2. The power consumption of the transmitter and receiver are 6 and 5 mW, respectively, when the output power level of the transmitter is 0 dBm. The noise figure of Rx is up to 6.8 dB with respect to channel frequencies. The phase noise of the ADPLL is −84.7 and −118.9 dBc/Hz at 100 kHz and 1 MHz offset from 2.44 GHz, respectively.