Hong Yu

The Study of Effective Work Function Modulation by As Ion Implantation in TiN/TaN/HfO2 Stacks

The impact on the metal gate effective work function (EWF) of As ion implantation through TiN/TaN/HfO2 gate stack was investigated. An As implantation at 20 KeV reduces the flat-band voltage (VFB) for TiN/TaN/HfO2 capacitors (or equivalently reduces the EWF) by a maximum of 600 mV at a dose of 5×1015 cm-2. This VFB reduction is correlated to the As pile-up at the TaN–HfO2 interface, as evidenced by a secondary ion mass spectroscopy (SIMS) study. The As ion accumulation at the interface of the gate electrode–dielectric interface is suggested to induce an interface dipole, contributing to the observed phenomena.

Understanding and prediction of EWF modulation induced by various dopants in the gate stack for a gate-first integration scheme

For the first time, after considering the thermodynamic properties (evaluated by the molar Gibbs energy of oxide formation, DeltaOxideG) and the electronegativity (chi) for both the dopants (via ion implantation, thin capping layer or co-deposition) and host materials in the gate stack, a practical model to understand the effective work function (EWF) modulation induced by various dopants is proposed. It is found that the dopant oxide will determine the EWF if the DeltaOxideG of dopant (DeltaOx-dopG) is more negative than that of host gate oxide (DeltaOx-hostG). Or else, chi difference between dopants and host materials will play a more critical role for determining the EWF. This model can serve as a guideline for understanding the EWF modulation by various dopants and to select appropriate gate stack materials for the gate-first technology.

Demonstration of phase-controlled Ni-FUSI CMOSFETs employing SiON dielectrics capped with sub-monolayer ALD HfSiON for low power applications

In this work, by employing a sub-monolayer HfSiON cap (via ALD deposition) on the SiON host dielectrics in the phase-controlled Ni-FUSI CMOS devices, we report that 1) the devices (both n-FETs and p-FETs) V, is effectively modulated likely due to the Fermi-level pinning relaxation; 2) the gate leakage is significantly reduced; 3) the dielectrics reliability characteristics (such as TZBD, pFETs NBTI, and nFETs PBTI) are clearly improved; 4) both the gate capacitance equivalent thickness (Tinv) and the long channel device high Eeff mobility are preserved. High-Vt ring oscillator with a delay of 17ps has been demonstrated, showing a much-reduced static power (~10 times) as compared to the devices using the pure SiON dielectrics. It is proposed that the SiON dielectrics capped with sub-monolayer HfSiON, in combination with the phase-controlled Ni-FUSI technology, is promising for 45 nm and beyond low power CMOS applications.

Experimental and simulation study of the Schottky barrier lowering by substrate doping variation for PtSi Source/Drain SBFETs

In this paper, the authors study experimentally and numerically the Schottky barrier height (SBH) lowering of Pt silicide/n-Si diodes and its implications to Schottky-barrier (SB) source/drain p-FETs. The authors demonstrate that hole SBH can be lowered through an image-force mechanism by increasing the n-Si substrate doping, which leads to a substantial gain of the drive current in the long-channel bulk p-SBFETs. Numerical simulations show that the channel doping concentration is also critical for short-channel n- & p-SOI SBFETs performance

Gate-dielectric interface effects on low-frequency (1/f) noise in p-MOSFETs with high-K dielectrics

Introduction: Aggressive scaling of MOSFETs has led to the implementation of Hf-based high-K dielectric materials as an alternative to SiO2 gate oxides for CMOS technologies. Metal-gate and FUSI electrode materials, due to reduced poly-depletion and remote scattering effects, are considered for replacing poly-Si gate electrodes. These changes are seen to have a fundamental impact on 1/f noise performance [1]. For the first time, we show that the 1/f noise is affected by the gate-dielectric interface. This is done by studying poly-Si, metal and undoped FUlly nickel SIlicided (FUSI) gate electrodes on pure SiON, Hf-silicate and HfO2 dielectric p-MOSFETs. Results and Discussion: The noise was measured on 10 μm x 1 μm p-MOSFETs in linear (|VDS| = 0.05 V) regime with the gate bias changed from weak to strong inversion. EOT of the devices is 1.5nm±0.2nm. Fig. 1 shows the ID-VG and GM-VG characteristics of TiN-TaN (metal), poly-Si, NiSi (FUSI) gate electrodes on 55% Hf-silicate gate dielectrics. A higher VT shift and lower GM is observed for poly-Si MOSFETs while metal and FUSI performances are quite comparable, which is mainly attributed to work-function shift of the gate electrode material. Figs 2, 3 and 4 represent