Caroline Demeurisse

Silicides for the 100-nm node and beyond: Co-silicide, Co(Ni)-silicide and Ni-silicide

As scaling progresses, conventional Co/Ti silicidation is facing difficulties related to the nucleation of the low resistive Co-disilicide phase during the second RTP step of silicidation. When linewidths, junction depths and silicide thicknesses are being reduced, the RTP2 thermal process window narrows down rapidly. It is expected that the process window can be widened by alloying the Co film with Ni, because the presence of Ni lowers the nucleation barrier for the Co-disilicide phase. Replacing Co-disilicide by Ni-monosilicide is a promising alternative because the same silicide sheet resistance can be obtained with 35% less silicon consumption.

Scalability of Ni FUSI gate processes: phase and Vt control to 30 nm gate lengths

We demonstrate for the first time the scalability of NiSi and Ni/sub 3/Si FUSI gate processes down to 30 nm gate lengths, with linewidth independent phase and V/sub t/ control. We show that 1-step FUSI is inadequate for NiSi FUSI gates, because it results in incomplete silicidation at low thermal budgets or in a linewidth dependent Ni silicide phase - inducing V/sub t/ shifts - at higher thermal budgets. We show that V/sub t/ and WF shifts are larger on high-K (HfO/sub 2/ (250 mV) or HfSiON (330mV)) than on SiON (110mV) and report Fermi level unpinning for Ni-rich FUSI on high-K. In contrast, we demonstrate the scalability of Ni/sub 3/Si FUSI, with no phase control issues, and report HfSiON Ni/sub 3/Si FUSI PMOS devices with V/sub t/= -0.33 V. Lastly, we show that, for NiSi, phase control down to narrow gate lengths can be obtained with a 2-step FUSI process.

Impact of bottom electrode and SrxTiyOz film formation on physical and electrical properties of metal-insulator-metal capacitors

Metal-insulator-metal capacitors with SrxTiyOz (STO) dielectric films on TiN, Ru, and RuOx bottom electrodes with TiN top electrodes were studied. Metastable perovskite STO films with compositions in the Sr/(Sr+Ti)∼54–64 at. % range were obtained by crystallization at 600 °C in N2 of dielectric stacks grown by atomic layer deposition consisting of Sr-rich STO films [Sr/(Sr+Ti)∼64 at. %] on thin interfacial TiOx layers. The significant decrease in equivalent oxide thickness (EOT) and STO lattice parameter observed with increasing TiOx thickness indicates full intermixing of the TiOx and STO layers during the crystallization anneal, which results in the formation of an STO layer with higher Ti content and higher dielectric constant. The Sr-rich STO on TiOx stacks crystallize with small grain size, favorable for low leakage (JG). A significant improvement in JG for e-injection from the bottom electrode is obtained when using RuOx, as compared to TiN or Ru. A milder JG improvement with RuOx bottom electrode i...

Impact of crystallization behavior of SrxTiyOz films on electrical properties of metal-insulator-metal capacitors with TiN electrodes

Metastable perovskite SrxTiyOz (STO) films were formed over a wide composition range by crystallization of layers grown by atomic layer deposition. An expansion of the lattice, decrease in permittivity and mild increase in band gap are observed with increasing Sr content. Sr-rich films [Sr/(Sr+Ti)∼62 at. %] show significant improvement in leakage current at low equivalent oxide thicknesses (EOT) as compared to stoichiometric films (Sr/(Sr+Ti) ∼50 at. %). TiN/STO/TiN capacitors with leakage ∼10−6 A/cm2 at 1 V were obtained at 0.6 nm EOT for crystalline Sr-rich STO. The difference in leakage behavior was found to correlate with different microstructures developed during crystallization.

Defect Removal, Dopant Diffusion and Activation Issues in Ion-Implanted Shallow Junctions Fabricated in Crystalline Germanium Substrates

The formation of shallow junctions in germanium substrates, compatible with deep submicron CMOS processing is discussed with respect to dopant diffusion and activation and damage removal. Examples will be discussed for B and Ga and for P and As, as typical p- and n-type dopants, respectively. While 1 to 60 s Rapid Thermal Annealing at temperatures in the range 400-650oC have been utilized, in most cases, no residual extended defects have been observed by RBS and TEM. It is shown that 100% activation of B can be achieved in combination with a Ge pre-amorphisation implant. Full activation of a P-implant can also be obtained for low-dose implantations, corresponding with immobile profiles. On the other hand, for a dose above the threshold for amorphisation, a concentration-enhanced diffusion of P occurs, while a lower percentage of activation is observed. At the same time, dose loss by P out-diffusion occurs, which can be limited by employing a SiO2 cap layer.

Work function of Ni3Si2 on HfSixOy and SiO2 and its implication for Ni fully silicided gate applications

The effective work function (WF) of Ni3Si2 was evaluated on HfSixOy and SiO2 dielectrics. Ni3Si2 forms, in thin film Ni–Si diffusion couples with Ni to Si composition ratios between 1 and 2, after formation of a Ni2Si∕NiSi stack and by its reaction at moderate thermal budgets (comparable to those used in back end processing of complementary metal-oxide-semiconductor circuits). Ni3Si2 formation limits, on the Ni-rich side, the process window for NiSi fully silicided (FUSI) gates (NiSi at interface with dielectric) to reacted Ni–Si ratios <1.5. The WF of Ni3Si2 was found to have similar values and behavior to that of NiSi, both on SiO2 (showing similar modulation with dopants) and on HfSixOy, in contrast to Ni-richer silicides such as Ni2Si and Ni31Si12 which do not exhibit significant WF modulation with dopants on SiO2 and have considerably higher WF on HfSixOy. This suggests that the chemistry and structure of the original NiSi/dielectric interface are not modified significantly by the subsequent growth o...

Kinetics of Ni3Si2 formation in the Ni2Si–NiSi thin film reaction from in situ measurements

The kinetics of Ni3Si2 formation in the Ni2Si–NiSi thin film reaction were determined from simultaneous in situ x-ray diffraction (XRD) measurements, performed using a synchrotron source, and sheet resistance measurements. Samples consisted of 90nm Ni∕100nm polycrystalline-Si∕SiO2 stacks, of interest for fully silicided gate applications, on (100) Si. After initial formation of a Ni2Si∕NiSi bilayer, these films reacted to form Ni3Si2. The evolution of sheet resistance and of the intensity of XRD peaks were used to extract the fraction of Ni3Si2 formed during ramp and isothermal annealings. A Kissinger analysis was performed for ramp annealing with ramp rates of 1, 3, 5, 9, and 27°C∕s, obtaining the activation energy of Ni3Si2 formation, Ea=1.92±0.15eV. A Kolmogorov-Johnson-Mehl-Avrami analysis was performed for isothermal anneals, finding an Avrami exponent of 2.1±0.2, suggesting two-dimensional growth. This is consistent with a nucleation controlled process for Ni3Si2 formation, with nucleation sites at ...

Transient and end silicide phase formation in thin film Ni/polycrystalline-Si reactions for fully silicided gate applications

The Ni/polycrystalline-Si thin film reaction was monitored by in situ x-ray diffraction during ramp annealings, obtaining a detailed view of the formation and evolution of silicide phases in stacks of interest for fully silicided gate applications. Samples consisted of Ni (30–170nm)/polycrystalline-Si (100nm)∕SiO2 (10–30nm) stacks deposited on (100) Si. The dominant end phase (after full silicidation) was found to be well controlled by the deposited Ni to polycrystalline-Si thickness ratio (tNi∕tSi), with formation of NiSi2 (∼600°C), NiSi (∼400°C), Ni3Si2 (∼500°C), Ni2Si, Ni31Si12 (∼420°C), and Ni3Si (∼600°C) in stacks with tNi∕tSi of 0.3, 0.6, 0.9, 1.2, 1.4, and 1.7, respectively. NiSi and Ni31Si12 were observed to precede formation of NiSi2 and Ni3Si, respectively, as expected for the phase sequence conventionally reported. Formation of Ni2Si was observed at early stages of the reaction. These studies revealed, in addition, the formation of transient phases that appeared and disappeared in narrow temper...

Direct evidence of linewidth effect: Ni31Si12 and Ni3Si formation on 25nm Ni fully silicided gates

The Ni silicidation of polycrystalline-Si∕SiO2 gates with 25nm linewidth was studied by x-ray diffraction and compared to that of blanket films. The authors found direct evidence of a linewidth effect in Ni full silicidation (FUSI), with formation of Ni-richer silicides at short gate lengths, and attribute it to the excess availability of Ni from regions surrounding the gate. On blanket films, the end silicide phase can be controlled by the deposited Ni (tNi) and polycrystalline-Si (tSi) thicknesses (e.g., tNi∕tSi∼0.55, 1.09, 1.37, and 1.64 for stoichiometric NiSi, Ni2Si, Ni31Si12, and Ni3Si, respectively). In contrast, they demonstrate that on 25nm lines, the resulting films can contain Ni31Si12 and Ni3Si even for deposited tNi∕tSi as low as 0.6. They found, however, that the phase formation sequence and required thermal budgets were similar on 25nm lines (tNi∕tSi∼0.6 and 1.2) to those on blanket films with thicker Ni (tNi∕tSi∼1.7). This suggests that the nucleation and phase formation kinetics of Ni sil...

Challenges and solutions on pre-assembly processes for thinned 3D wafers with micro-bumps on the backside

In 3D IC technology, temporary bonding systems and stacking/assembly process are identified as critical elements given all the concerns on wafer handling amidst BEOL processes and how to do the stacking as best as one could in so many different schemes. In between the temporary bonding systems and stacking/assembly process, is a group and series of processes that link the two. This is collectively and commonly known as the pre-assembly process. This paper presents the in-house pre-assembly 3D IC process flow for thinned wafer with micro-bumps on the backside along with the different challenges on materials and processes on each step. Most importantly, this paper reports on a solution found that enabled pre-assembly process to successfully provide a bridge from temporary bonding systems to stacking/assembly process: a UV dicing tape that can handle the complexities at hand when processing thinned 3D IC wafers with backside micro bumps in pre-assembly integration.