Anne Lauwers

Materials aspects, electrical performance, and scalability of Ni silicide towards sub-0.13 μm technologies

Ni-silicide phase formation with and without a Ti capping layer was studied by sheet resistance, x-ray diffraction and transmission electron microscopy. Ni monosilicide is found to be the stable phase in a temperature range from 400 to 600 °C. At lower temperatures the Ni2Si phase is found to be present. For temperatures higher than 700 °C NiSi is converted into NiSi2. Pyramidal NiSi2 precipitates were found to grow epitaxially along the Si〈111〉 planes for annealing temperatures as low as 310 °C. The epitaxial NiSi2 grains were found to disappear when the annealing temperature is increased. Stress buildup during Ni silicidation was measured in situ and could be correlated to the formation of the different Ni-silicide phases. The stress induced by Ni-monosilicide formation compares favorably to the stress induced by Co disilicide and Ti disilicide. The average silicon consumption required to obtain a certain sheet resistance was found to be 35% lower for Ni monosilicide compared for Co disilicide. It was f...

Ni- and Co-based silicides for advanced CMOS applications

The scaling behavior of Co, Co-Ni and Ni silicides to sub-40 nm gate length CMOS technologies with sub-100 nm junction depths was evaluated. Limitations were found for Co and Co-Ni alloy silicides, which exhibited an increase in sheet resistance at gate lengths below 40 nm and required high processing temperatures to achieve low junction leakage. Ni silicide was shown, in contrast, to have good scaling behavior, with a decrease in sheet resistance for decreasing gate lengths down to 30 nm, lower diode leakage (at similar sheet resistance) and lower silicide to p+ Si contact resistance than Co silicide. Key material issues impacting the applicability of NiSi to CMOS technologies were investigated. Studies of the kinetics of Ni2Si growth were used to design a process that avoids excessive silicidation of small features. The thermal degradation mechanisms of NiSi films were also studied. Thin films degraded morphologically with activation energies of ∼ 2.4 eV. Thick films degraded morphologically at low temperatures and by transformation to NiSi2 at high temperatures, suggesting a higher activation energy for the latter mechanism. Pt alloying was shown to help stabilize NiSi films against morphological degradation.

In situ transmission electron microscopy study of Ni silicide phases formed on (001) Si active lines

The formation of Ni silicides is studied by transmission electron microscopy during in situ heating experiments of 12 nm Ni layers on blanket silicon, or in patterned structures covered with a thin chemical oxide. It is shown that the first phase formed is the NiSi2 which grows epitaxially in pyramidal crystals. The formation of NiSi occurs quite abruptly around 400 °C when a monosilicide layer covers the disilicide grains and the silicon in between. The NiSi phase remains stable up to 800 °C, at which temperature the layer finally fully transforms to NiSi2. The monosilicide grains show different epitaxial relationships with the Si substrate. Ni2Si is never observed.The formation of Ni silicides is studied by transmission electron microscopy during in situ heating experiments of 12 nm Ni layers on blanket silicon, or in patterned structures covered with a thin chemical oxide. It is shown that the first phase formed is the NiSi2 which grows epitaxially in pyramidal crystals. The formation of NiSi occurs quite abruptly around 400 °C when a monosilicide layer covers the disilicide grains and the silicon in between. The NiSi phase remains stable up to 800 °C, at which temperature the layer finally fully transforms to NiSi2. The monosilicide grains show different epitaxial relationships with the Si substrate. Ni2Si is never observed.

Silicides for the 100-nm node and beyond: Co-silicide, Co(Ni)-silicide and Ni-silicide

As scaling progresses, conventional Co/Ti silicidation is facing difficulties related to the nucleation of the low resistive Co-disilicide phase during the second RTP step of silicidation. When linewidths, junction depths and silicide thicknesses are being reduced, the RTP2 thermal process window narrows down rapidly. It is expected that the process window can be widened by alloying the Co film with Ni, because the presence of Ni lowers the nucleation barrier for the Co-disilicide phase. Replacing Co-disilicide by Ni-monosilicide is a promising alternative because the same silicide sheet resistance can be obtained with 35% less silicon consumption.

Demonstration of fully Ni-silicided metal gates on HfO/sub 2/ based high-k gate dielectrics as a candidate for low power applications

We have fabricated fully Ni-silicided metal gate (FUSI) CMOS devices with HfO2-based gate dielectrics for the first time. We demonstrate that full silicidation eliminates the Fermi level pinning at the polySi-HfO2 dielectric interface in pFETs. For nMOS devices, a 5 orders of magnitude reduction in short channel sub-threshold leakage is obtained with similar drive current compared to the poly gate devices. In addition, the FUSI process does not degrade the hysterisis nor the dielectric breakdown. This result makes FUSI on high-K a strong candidate for scaled low power technologies.

A Comparison of Spike, Flash, SPER and Laser Annealing for 45nm CMOS

Due to integration concerns, the use of meta-stable junction formation approaches like laser thermal annealing (LTA), solid phase epitaxial regrowth (SPER), and flash annealing has largely been avoided for the 90nm CMOS node. Instead fast-ramp spike annealing has been optimised along with co-implantation to satisfy the device requirements, often with the help from thin offset spacers. However for the 65nm and 45nm CMOS node it is widely accepted that this conventional approach will not provide the required pMOS junctions, even with changes in the transistor architecture. In this work, we will compare junction performance and integratablity of fast-ramp spike, flash, SPER and laser annealing down to 45nm CMOS. The junction depth, abruptness and resistance offered by each approach are balanced against device uniformity, deactivation and leakage. Results show that the main contenders for the 45nm CMOS are SPER and flash annealing – but both have to be rigorously optimised for regrowth rates, amorphous positioning and dopant and co-implant profiles. From the two, SPER offers the best junction abruptness ( 4E20at/cm3) and less transistor modifications. As expected, Ge and F co-implanted spike annealed junctions do not reach the 45nm node requirements. For full-melt LTA, poly deformation on isolation can be reduced but geometry effects result in unacceptable junction non-uniformity.

Comparative study of Ni-silicide and Co-silicide for sub 0.25-mm technologies

In this work, the phase formation is compared for Ni- and Co-silicidation with and without Ti cap. In addition, the electrical performance of Ni-silicidation with and without Ti-cap is investigated and compared to the performance of a Co-silicidation process with a Ti cap that has the same Si consumption. The lateral confinement of the silicide in the active areas is also studied.

Thickness scaling issues of Ni silicide

Ni silicidation processes without a capping layer and with a TiN capping layer are studied from the point of view of process window, morphology of the resulting silicide, and mechanisms of degradation at higher temperatures. The thermal stability of NiSi films on As- and on B-doped (100) Si substrates was investigated for Ni film thicknesses ranging from 5 to 30 nm. While agglomeration was the mechanism of degradation for the thin films, both morphological changes and transformation to NiSi2 were possible for thicker films depending on anneal temperature and time. Activation energy of ∼2.5 eV for NiSi on n+ (100) Si and p+ (100) Si was determined for the process of morphological degradation. The measured temperature and time dependences for the thermal degradation of NiSi films suggest that the activation energy for transformation to NiSi2 is higher than for morphological degradation.

CMOS integration of dual work function phase controlled Ni FUSI with simultaneous silicidation of NMOS (NiSi) and PMOS (Ni-rich silicide) gates on HfSiON

We demonstrate for the first time CMOS integration of dual WF (work function) metal gates on HfSiON using Ni-phase controlled FUSI. The novel integration scheme that we demonstrate uses our optimized 2-step Ni FUSI process (1) for simultaneous full silicidation of nMOS and pMOS, achieving different Ni/Si ratios on nMOS and pMOS by reduction of the pMOS poly height through a selective and controlled poly etch back prior to gate silicidation. This novel integration scheme offers the advantages of 1) simplicity (same Ni deposition and silicidation process on nMOS and pMOS), 2) large process window for poly etch-back process (same pMOS characteristics for poly thickness variation of 50%), 3) WF and Vt tuning on HfSiON by phase control, with 4) scalable, linewidth independent suitable Vts for nMOS (0.5 V) and pMOS (-0.3 V), and 5) solves process yield issues of Ni-rich silicides related to volume expansion, stress, filaments and voiding, resulting in a continuous silicide that is nicely confined between the sidewall spacers. Ring oscillator operation was also demonstrated

Technological aspects of epitaxial CoSi2 layers for CMOS

Abstract The use of consecutively sputtered Ti/Co layers for the silicidation of Si implanted with 2 × 1015 As or B/cm2 and for the silicidation of polycrystalline Si has been investigated. It has been observed that the silicidation reaction is slowed down by the presence of the Ti layer, which acts as a diffusion barrier. The use of a Ti/Co bilayer leads to the growth of epitaxial CoSi2 layers on implanted silicon with very smooth CoSi2/Si interfaces and an excellent thermal stability. In addition, the silicide formation on poly-Si gate lines has been studied. It has been found that amorphisation of poly-Si prior to metal deposition prevents the lateral overgrowth of the silicide on the oxide spacers during silicidation.