Hossein Elahipanah

5.8-kV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension

Implantation-free 4H-SiC bipolar junction transistors with multiple-shallow-trench junction termination extension have been fabricated. The maximum current gain of 40 at a current density of 370 A/cm² is obtained for the device with an active area of 0.065 mm². A maximum open-base breakdown voltage (BV) of 5.85 kV is measured, which is 93% of the theoretical BV. A specific ON-resistance (R_ON) of 28 mΩ·cm² was obtained.

Optimal Emitter Cell Geometry in High Power 4H-SiC BJTs

Three 4H-SiC bipolar junction transistor designs with different emitter cell geometries (linear interdigitated fingers, square cell geometry, and hexagon cell geometry) are fabricated, analyzed, and compared with respect to current gain, ON-resistance (RON), current density (JC), and temperature performance for the first time. Emitter size effect and surface recombination are investigated. Due to a better utilization of the base area, optimal emitter cell geometry significantly increases the current density about 42% and reduces the ON-resistance about 21% at a given current gain, thus making the device more efficient for high-power and high-temperature applications.

Area- and efficiency-optimized junction termination for a 5.6 kV SiC BJT process with low ON-resistance

Implantation-free mesa-etched 4H-SiC bipolar junction transistors (BJTs) with a near-ideal breakdown voltage of 5.6 kV (about 92% of the theoretical value) are fabricated, measured and analyzed by device simulation. An efficient and optimized termination; area-optimized three-zone junction termination extension (O-JTE) is implemented, reducing the total area (and substrate cost) by about 30% compared to the traditional JTE designs. A maximum current gain of β = 44 at a current density of 472 A/cm², and a specific on-resistance of R_ON = 18.8 mΩ.cm² is obtained for the device. The device shows a negative temperature coefficient of the current gain (β = 14.5 at 200 °C) and a positive temperature coefficient of on-resistance (R_ON = 57.3 mΩ·cm² at 200 °C).

Area-Optimized JTE for 4.5 kV Non Ion-Implanted 4H-SiC BJT

Non ion-implantation mesa etched 4H-SiC BJT with three-zone JTE of optimized lengths and doses (descending sequences) has been simulated. This design presents an efficient electric field distribution along the device. The device area has been optimized and considerably reduced. As a result of this comprehensive optimization, a high breakdown voltage and high current gain have been achieved; meanwhile the device area with a constant emitter and base contact area has been reduced by about 30%.

Modification of Etched Junction Termination Extension for the High Voltage 4H-SiC Power Devices

High voltage 4H-SiC bipolar junction transistors (BJTs) with modified etched junction termination extension (JTE) were fabricated and optimized in terms of the length (LJTE) and remaining dose (DJTE) of JTEs. It is found that for a given total termination length (Σ LJTEi), a decremental JTE length from the innermost edge to the outermost mesa edge of the device will result in better modification of the electric field. A breakdown voltage (BV) of 4.95 kV is measured for the modified device which shows ~20% improvement of the termination efficiency for no extra cost or extra process step. Equal-size BJTs by interdigitated-emitter with different number of fingers and cell pitches were fabricated. The maximum current gain of 40 is achieved for a single finger device with the emitter width of 40 µm at IC = 0.25 A (JC = 310 A/cm2) which corresponds to RON = 33 mΩ.cm2. It is presented that the current gain decreases by having more fingers while the maximum current gain is achieved at higher current density.

Conductivity modulated on-axis 4H-SiC 10+ kV PiN diodes

Degradation-free ultrahigh-voltage (>10 kV) PiN diodes using on-axis 4H-SiC with low forward voltage drop (V_F = 3.3 V at 100 A/cm²) and low differential on-resistance (R_ON = 3.4 mΩ.cm²) are fabricated, measured, and analyzed by device simulation. The devices show stable on-state characteristics over a broad temperature range up to 300 °C. They show no breakdown up to 10 kV, i.e., the highest blocking capability for 4H-SiC devices using on-axis to date. The minority carrier lifetime (τ_P) is measured after epitaxial growth by time resolved photoluminescence (TRPL) technique at room temperature. The τ_P is measured again after device fabrication by open circuit voltage decay (OCVD) up to 500 K.

Geometrical Effect Dependency on the On-State Characteristics in 5.6 kV 4H-SiC BJTs

The influence of varying the emitter-base geometry, i.e., the emitter width (WE), emitter contact–emitter edge distance (Wn), and base contact–emitter edge (Wp) on the on-state characteristics in 5.6 kV implantation free 4H-SiC BJTs are investigated. The BJTs present a clear emitter size effect pointing out that surface recombination has a significant influence on current gain (β). The results show that the influence of varying Wp on the β is higher than Wn. A distance of 3 μm between emitter contact and base contact to the emitter edge (Wn = Wp = 3 μm) is the optimized value to have a BJT with a high β, and low on-resistance (RON) at a given WE.

Investigation of the breakdown voltage in high voltage 4H-SiC BJT with respect to oxide and interface charges

Ion implantation in silicon carbide (SiC) induces defects during the process. Implantation free processing can eliminate these problems. The junction termination extension (JTE) can also be formed without ion implantation in SiC bipolar junction transistor (BJT) using a well-controlled etching into the epitaxial base layer. The fixed charges at the SiC/SiO2 interface modify the effective dose of the JTEs, leakage current, and breakdown voltage. In this paper the influence of fixed charges (positive and negative) and also interface trap density at the SiC/SiO2 interface on the breakdown voltage in 4.5 kV 4H-SiC non-ion implanted BJT have been simulated. SiO2 as a surface passivation layer including interface traps and fixed charges has been considered in the analysis. Simulation result shows that the fixed charges influence the breakdown voltage significantly more than the interface traps. It also shows that the positive fixed charges reduce the breakdown voltage more than the negative fixed charges. The combination of interface traps and fixed charges must be considered when optimizing the breakdown voltage.

Intertwined Design: A Novel Lithographic Method to Realize Area Efficient High-Voltage SiC BJTs and Darlington Transistors

A novel lithographic method called intertwined design is demonstrated for high-power SiC devices to improve the area usage and current drive with more uniform current distribution along the device. The higher current drive is achieved by employing the inactive area underneath the base metal contact pads; more uniform current distribution is obtained by the center-base design; whereas the hexagon and square cell geometries result in >15% higher current density at lower on-resistance compared with the conventional finger design. For the first time, we have experimentally presented the intertwined design to marry these advantages and realize a high-efficient SiC power device. Center-base high-voltage 4H-SiC BJTs and Darlington pairs with different square and hexagon cell geometries are fabricated and compared with conventional designs to prove the ability of the intertwined design. The method can widely be used for large-area high-voltage BJTs as well as for integrated devices.

4.5-kV 20-mΩ.cm2 Implantation-Free 4H-SiC BJT with Trench Structures on the Junction Termination Extension

A single-mask junction termination extension withtrench structures is formed to realize a 4.5 kV implantation-free 4H-SiCbipolar junction transistor (BJT). The trench structures are formed on the baselayer with dry etching using a single mask. The electric field distributionalong the structure is controlled by the number and dimensions of the trenches.The electric field is distributed by the trench structures and thus the electricfield crowding at the base and mesa edges is diminished. The design isoptimized in terms of the depth, width, spacing, and number of the trenches toachieve a breakdown voltage (VB) of 4.5 kV, which is 85% of thetheoretical value. Higher efficiency is obtainable with finer lithographicresolution leading to smaller pitch, and higher number and narrower trenches.The specific on-resistance (RON) of 20 mΩ.cm2 is measuredfor the small-area BJT with active area of 0.04 mm2. The BV-RONof the fabricated device is very close to the SiC limit and by far exceeds thebest SiC MOSFETs.