Houda Daoud

Design of a low power Variable Gain Amplifier for WLAN standard

This paper presents the design of Variable Gain Amplifier (VGA) circuit intended to be used for WLAN receiver. The proposed circuit is composed of two transimpedance amplifiers and a transconductance amplifier. The gain tuning is achieved by using an active resistor. The VGA control is ensured by using a voltage-controlled active resistor VG. The proposed circuit is optimized for low power, low noise and high bandwidth application. This circuit is implemented and simulated using the TSMC 0.18 µm CMOS process device-level description. The studied circuit provided a minimum gain of 6dB and a maximum gain of 51.2dB over more than 66MHz bandwidth. The simulation structure provides less than 17dB of noise figure (NF), an Input Referred Noise (IRN) of around 2.4nV2/Hz, an output Referred Noise (ORN) of around 13.32nV2/Hz and a Third Order Intercept Point measured at the Input (IIP3) of −6dBm. The VGA consumes approximately 70µW under 1.8V power supply.

Low-power CMOS Variable Gain Amplifier design in 0.18µm process

This paper presents a low-power Variable Gain Amplifier (VGA) design in TSMC 0.18μm process. The proposed circuit is composed of tow transimpedance amplifiers and a transconductance amplifier. The VGA control is ensured by using the source degeneration RS with the feedback resistor Rf. The proposed circuit is designed for low power, low noise and high bandwidth. The studied circuit provides a minimum and a maximum gain of respectively -33 dB and 25.6 dB over more than 133MHz bandwidth. The simulation structure provides less than 20 dB of noise figure (NF). The VGA consumes approximately 40μW under 1V power supply.

Wide band LC VCO with automatic amplitude controller for IEEE 802.22 cognitive radio receiver

This paper deals with the design of an LC Voltage Controlled Oscillator (LC VCO) with and without an Automatic Amplitude Controller (AAC). In order to achieve a wide band tuning range specified in IEEE 802.22 the VCO core incorporates a Switched Capacitor Array (SCA). An amplitude controlling technique is used to stabilize the oscillation amplitude over the frequency band. The LC VCO with an AAC circuit achieves 63% of tuning range and displays phase noise levels from -126.2 dBc/Hz to -122.67 dBc/Hz at 1 MHz frequency offset within the entire tuning range. The average power consumption of the oscillator with an AAC is 21 mW.

Design Methodology of High-Order Feed-Forward ΔΣ Modulators for Broadband Communications

This paper presents a design methodology to optimize high order Feed-Forward (FF) Delta-Sigma (ΔΣ) modulators architectures intended for use in next generations wireless applications. Being a low power and a low noise basic building block, the Telescopic OTA circuit is optimized using an algorithmic driven methodology to implement the switched capacitor (SC) integrator which constitutes a fundamental component of the designed FF ΔΣ modulator. A 2-1-1 cascaded FF ΔΣ modulator is firstly, designed for WCDMA and WLAN standards. The FF ΔΣ modulator performances are improved by implementing a 2-2 cascaded FF ΔΣ modulator. Both system-level and transistor-level simulations were performed with MATLAB and ORCAD PSPICE (AMS 0.35µm CMOS process). The 2-1-1 and the 2-2 cascaded FF ΔΣ modulators implemented with optimized SC circuits achieve respectively SNRs of 50dB and 56.3dB with over-sampling ratio of 16 for WCDMA standard.

A CMOS Low-Power Digital Variable Gain Amplifier Design for a Cognitive Radio Receiver “Application for IEEE 802.22 Standard”

This paper presents the design of a new Digital Variable Gain Amplifier cell (DVGA). The proposed circuit based on transconductance, gm, amplifier and a transconductance amplifier is analyzed and d...

Optimizing CMOS analog Variable Gain Amplifier cell for WiMAX receiver

This paper presents the design of an analog Variable Gain Amplifier (VGA) design in TSMC 0.18 μm process. The proposed circuit is composed of tow transimpedance amplifiers, a transconductance amplifier applied to mobile WiMAX standard. The VGA control is ensured by using analog voltage control (Vctr). The optimized circuit presents high gain, high bandwidth, low power consumption and low Noise Figure (NF). In order to attempt mobile WiMAX standard specifications, one VGA cell is used. The simulation structure provides a minimum and a maximum gain of respectively 5 dB and 40 dB over more than 160 MHz bandwidth and less than 19 dB of NF. The VGA consumes only approximately 72 μW under 1.8 V power supply.

Design of discret time feed-forward cascaded ΔΣ modulator for wireless communication systems

This paper presents the design of discret time (DT) feed-forward (FF) 2-1 cascaded Delta-Sigma (ΔΣ) modulator used in wireless communication systems. This topology can provide several advantages over other architectures because of its relaxed requirements on the analog building blocks, mainly on the switched capacitor (SC) integrator. The design is performed by using optimized Telescopic and Gain-boosted OTAs to implement the integrator. Using AMS 0.35µm CMOS process, transistor-level simulation results indicate that the 2-1 cascaded ΔΣ modulator achieves a SNR of 47.5dB and 42dB over bandwidths of 2MHz and 3.84MHz respectively with over-sampling ratio of 16.

USE OF ROBUST PREDICTIVE METHOD FOR NANO-CMOS PROCESS: APPLICATION TO BASIC BLOCK ANALOG CIRCUIT DESIGN

This paper deals with the prediction of primary parameters of CMOS transistor for upcoming process using the robust Bisquare Weights method which is able to provide solutions to the challenges of some parameters of Nanoscale CMOS. Predicted parameters for 45 nm to 22 nm process nodes are obtained in order to solve design challenges generated by Nanoscale process. These predicted primary parameters are helpful to estimate the performance of a basic element circuit having a key role in the design of upcoming analog systems. Comparisons between predictive technology model data and predicted parameters are used to check the validity of the used method. As a study case, we will detail the behavior of optimized telescopic operational transconductance amplifier performance with process scaling.

NanoCMOS folded cascode OTA performances prediction through least-square method

This paper deals with the prediction of folded cascode OTA performances using upcoming CMOS Nano-process. Thus, the least-square method (LSM) is used to predict the CMOS device primary parameters which are generated for 45nm to 22nm CMOS processes. The predicted parameters are comparable to available published data to check the strength of the used LSM Methodology. Then, the impact of Nanometer CMOS on OTA analog basic block design is highlighted. It shows the potentialities of future CMOS processes to provide high speed and high performances analog circuits to design new generation systems demanding very severe requirements.

Feed-forward ΔΣ modulators topologies design for broadband communications applications

This paper presents a design methodology for low-distortions (feed-forward) Delta-Sigma (ΔΣ) modulators topologies used in next generations wireless applications. Thus, optimized folded cascode OTA and telescopic OTA gain-boosting are selected to implement the switched capacitor (SC) integrator. First, a second order ΔΣ modulator is implemented for 2MHz bandwidth. Second, a 2–2 cascaded ΔΣ modulator is designed for 2MHz and 10MHz bandwidths in order to improve the modulator performances. These modulators are implemented using system-level simulations as well as device-level simulations implemented with SC circuits in AMS 0.35μm CMOS process. Device-level simulations results indicate that the 2nd and the 2–2 cascaded ΔΣ modulators achieve respectively SNRs of 43dB and 38dB over bandwidths of 2MHz and 10MHz with over-sampling ratios 16 and 8.