Samir Ben Salem

An optimized low voltage and High Frequency CCII based multifunction Filters

In this paper, a low voltage current conveyor (CCII) based multifunction filter is presented. Firstly, thanks to an optimizing heuristic, an optimal sizing of a low voltage low power CMOS current conveyor (CCII) was done. Hence, we improve static and dynamic performances of this configuration. The optimized CCII configuration has a current bandwidth of 1.103 GHz and a voltage bandwidth of 1.18 GHz and 33.4 Omega as RX parasitic resistance value. Secondly, implementation of a multifunction filter based on this configuration was done. The current mode Alter has a tunable central frequency in the range [50MHz-800MHz]. PSPICE simulations are presented to demonstrate these results.

A New CMOS Current Controlled Quadrature Oscillator Based on a MCCII

In this paper, we propose a design of a current controlled Quadrature Sinusoidal Oscillator. The proposed circuit employs three optimized Multi-output translinear second generation current conveyer (MCCII). The oscillation condition and the oscillation frequency are independently controllable. The proposed Quadrature Oscillator frequency can be tuned in the range of [198 MHz –261 MHz] by a simple variation of a DC current. PSpice simulation results are performed using CMOS 0.35 µm process of AMS.

A NOVEL CCII-BASED TUNABLE INDUCTANCE AND HIGH FREQUENCY CURRENT-MODE BAND PASS FILTER APPLICATION

In this paper, we introduce an implementation of a CCII-based grounded inductance operating in class AB. In order to get tunable characteristics of the design, a translinear CCII configuration is used as a basic block for its high level of controllability. A frequency characterization of the translinear CCII is done. In order to optimize its static and dynamic characteristics, an algorithmic driven methodology is developed ending to the optimal transistor geometries. The optimized CCII has a current bandwidth of 1.28 GHz and a voltage bandwidth of 5.48 GHz. It is applied in the simulated inductance design. We first consider the conventional topology of the grounded inductance based on the generalized impedance converter principle. Making use of the controllable series parasitic resistance at port X in translinear CCII, we design tunable characteristics of the inductance. The effect of current conveyors nonidealities has been taken into account. A compensation strategy has been presented. It is based on the insertion of a high active CCII-based negative resistance and a very low passive resistance. The compensation strategy does not affect the inductance tuning process. Simulation results show that the proposed inductance can be tuned in the range [0.025 μH; 15.4 μH]. The simulated inductance has been applied in a fully integrated tunable high frequency band pass filter to illustrate the versatility of the circuit. The filter is electrically tunable by controlling the conveyors bias current.

Low-power CMOS Variable Gain Amplifier design in 0.18µm process

This paper presents a low-power Variable Gain Amplifier (VGA) design in TSMC 0.18μm process. The proposed circuit is composed of tow transimpedance amplifiers and a transconductance amplifier. The VGA control is ensured by using the source degeneration RS with the feedback resistor Rf. The proposed circuit is designed for low power, low noise and high bandwidth. The studied circuit provides a minimum and a maximum gain of respectively -33 dB and 25.6 dB over more than 133MHz bandwidth. The simulation structure provides less than 20 dB of noise figure (NF). The VGA consumes approximately 40μW under 1V power supply.

Design Methodology of High-Order Feed-Forward ΔΣ Modulators for Broadband Communications

This paper presents a design methodology to optimize high order Feed-Forward (FF) Delta-Sigma (ΔΣ) modulators architectures intended for use in next generations wireless applications. Being a low power and a low noise basic building block, the Telescopic OTA circuit is optimized using an algorithmic driven methodology to implement the switched capacitor (SC) integrator which constitutes a fundamental component of the designed FF ΔΣ modulator. A 2-1-1 cascaded FF ΔΣ modulator is firstly, designed for WCDMA and WLAN standards. The FF ΔΣ modulator performances are improved by implementing a 2-2 cascaded FF ΔΣ modulator. Both system-level and transistor-level simulations were performed with MATLAB and ORCAD PSPICE (AMS 0.35µm CMOS process). The 2-1-1 and the 2-2 cascaded FF ΔΣ modulators implemented with optimized SC circuits achieve respectively SNRs of 50dB and 56.3dB with over-sampling ratio of 16 for WCDMA standard.

A CMOS Low-Power Digital Variable Gain Amplifier Design for a Cognitive Radio Receiver “Application for IEEE 802.22 Standard”

This paper presents the design of a new Digital Variable Gain Amplifier cell (DVGA). The proposed circuit based on transconductance, gm, amplifier and a transconductance amplifier is analyzed and d...

Optimizing CMOS analog Variable Gain Amplifier cell for WiMAX receiver

This paper presents the design of an analog Variable Gain Amplifier (VGA) design in TSMC 0.18 μm process. The proposed circuit is composed of tow transimpedance amplifiers, a transconductance amplifier applied to mobile WiMAX standard. The VGA control is ensured by using analog voltage control (Vctr). The optimized circuit presents high gain, high bandwidth, low power consumption and low Noise Figure (NF). In order to attempt mobile WiMAX standard specifications, one VGA cell is used. The simulation structure provides a minimum and a maximum gain of respectively 5 dB and 40 dB over more than 160 MHz bandwidth and less than 19 dB of NF. The VGA consumes only approximately 72 μW under 1.8 V power supply.

Design of discret time feed-forward cascaded ΔΣ modulator for wireless communication systems

This paper presents the design of discret time (DT) feed-forward (FF) 2-1 cascaded Delta-Sigma (ΔΣ) modulator used in wireless communication systems. This topology can provide several advantages over other architectures because of its relaxed requirements on the analog building blocks, mainly on the switched capacitor (SC) integrator. The design is performed by using optimized Telescopic and Gain-boosted OTAs to implement the integrator. Using AMS 0.35µm CMOS process, transistor-level simulation results indicate that the 2-1 cascaded ΔΣ modulator achieves a SNR of 47.5dB and 42dB over bandwidths of 2MHz and 3.84MHz respectively with over-sampling ratio of 16.

Variable Gain Amplifier in CMOS 0.18µm for WiMAX application

A CMOS Variable Gain Amplifier (VGA) in TSMC 0.18μm technology is designed. The circuit is applied for IEEE 802.16e standard, mobile WiMAX. The used structure is based on differential pair with source-degeneration topology. Two VGA cells were cascaded in order to attend WiMAX requirements. The studied circuit provided a minimum gain of 4.87dB and a maximum gain of 40.19dB over more than 100MHz bandwidth. A noise figure less than 20dB is obtained. The VGA consumes approximately 10mW under ±0.75V power supply.

Feed-forward ΔΣ modulators topologies design for broadband communications applications

This paper presents a design methodology for low-distortions (feed-forward) Delta-Sigma (ΔΣ) modulators topologies used in next generations wireless applications. Thus, optimized folded cascode OTA and telescopic OTA gain-boosting are selected to implement the switched capacitor (SC) integrator. First, a second order ΔΣ modulator is implemented for 2MHz bandwidth. Second, a 2–2 cascaded ΔΣ modulator is designed for 2MHz and 10MHz bandwidths in order to improve the modulator performances. These modulators are implemented using system-level simulations as well as device-level simulations implemented with SC circuits in AMS 0.35μm CMOS process. Device-level simulations results indicate that the 2nd and the 2–2 cascaded ΔΣ modulators achieve respectively SNRs of 43dB and 38dB over bandwidths of 2MHz and 10MHz with over-sampling ratios 16 and 8.