Houssam Arbess

Combined MOS–IGBT–SCR Structure for a Compact High-Robustness ESD Power Clamp in Smart Power SOI Technology

Smart power technologies are required to withstand high-electrostatic-discharge (ESD) robustness under both powered and unpowered conditions, particularly for automotive and aeronautic applications among many others. They are concurrently confronted to the challenges of high-temperature operation in order to reduce heat-sink-related costs. In this context, very compact high-robustness ESD protections with low sensitivity to temperature are required. To fulfill this need, we studied a new ESD protection structure that combines in the same component MOS, IGBT, and thyristor effects. This is achieved by inserting in the same LDMOS device P+ diffusions in the drain. We studied the impact of N+/P+ ratios on RON and holding current at high temperatures. Structure optimization has been realized with 3-D TCAD simulation and experimentally validated. The proposed structures provide high ESD robustness with small footprint and reduced temperature sensitivity compared with classical solutions. Original design solutions to improve their immunity to latchup are also presented.

Field plate termination for high voltage diamond Schottky diode

New field plate architecture is applied to pseudo vertical diamond Schottky diode. New topology structure has been proposed and simulated using Sentaurus TCAD simulation in order to minimize the maximum electric field in the dielectric at high voltage operation. Firstly and after simple variations in the field plate architecture, the breakdown voltage was improved from 1632 V to 2141 V at 700 K. Concerning Emax in the dielectric, we obtained high decreasing of the maximum electric field following the policy of pressure distribution.

Optimization of a MOS–IGBT–SCR ESD protection component in smart power SOI technology

A MOS-IGBT-SCR component that was proposed in a previous paper to increase the device robustness and the cost of ESD protection circuit is optimized in this paper. In order to improve its latch up immunity, several variations of geometrical parameters that have been simulated using TCAD Sentaurus Device in another previous paper have been implemented and compared in this paper. The drift area, the form factor, and the proportion of P + sections inserted into the drain are the main parameters, which have a significant impact on the latch up immunity. TLP characterization, and curve tracer measurements have been carried out to evaluate the proposed solution. Holding current increases up to 70 mA and holding voltage up to 10 V. 1 Introduction The electrostatic discharge (ESD) has always been one of the highest reliability concerns in the integrated (IC) manufacturing industry. With the continuous miniaturization process, the integrated circuits become more and more vulnerable to ESD. The miniaturization of the ESD protection blocks is one of the greatest challenges of smart power technologies. Silicon On Insulator (SOI) technologies allow extending the operational temperature range while providing the necessary isolation between components with a reduced silicon area. SOI technology is becoming more and more attractive to manage very high voltage blocks, to reduce parasitic NPN effect and to increase Integrated Circuit (IC) speed as well as for applications operating at high temperature [1], [2]. Electro Static Discharge (ESD) protections occupy a significant silicon IC area. Using a LDMOS as main ESD protection component is not optimal due to its high on-resistance, but it could be the only solution for some technologies. In a previous work, we proposed a new ESD component (MOS-IGBT-SCR) and improved it in order to increase ESD performance and improve the latch up immunity [3] [4]. ESD performance was excellent but margin to prevent latch up was not satisfying. In this paper, an optimized version of this structure is discussed and experimentally validated. As the technological parameters of the used technology (TFSMART1: SOI smart power technology) cannot be changed, we explored various layout-design solutions such as the device topology or the architecture. 2 Structure description and preview solution

New termination architecture for 1700 V diamond Schottky diode

New field plate architecture is applied to pseudo vertical diamond Schottky diode. Using several field plate architectures, a TCAD simulation is realized in order to reduce the electric field in the dielectric while maintaining high breakdown voltage. Firstly and after simple variations in the field plate architecture, the breakdown voltage was improved from 1632 V to 2141 V at 700 K. Concerning Emax in the dielectric, we obtained a decreasing of maximum electric field from 57 to 18 MV/cm.

MOS-IGBT power devices for high-temperature operation in smart power SOI technology

Abstract We propose a new MOS-IGBT device with improved characteristics for high-temperature operation. It is achieved by inserting in the same LDMOS device P + diffusions in the drain with various N + /P + ratios. 3D TCAD simulations are used to optimize the original structure in particular, to validate drain and source engineering solutions aimed at providing a latch-up free operation.