Howard Chih-Hao Wang

Interface induced uphill diffusion of boron: an effective approach for ultrashallow junction

This paper investigates anomalous diffusion behavior for ultra low energy implants in the extension or tip of PMOS devices. Transient enhanced diffusion (TED) is minimal at these low energies, since excess interstitials are very close to the surface. Instead, interface induced uphill diffusion is found, for the first time, to dominate during low temperature thermal cycles. The interface pile-up dynamics can be taken advantage of to produce shallower junctions and improve short channel effect control in PMOS devices. Attempts to minimize TED before spacer deposition by inclusion of extra RTA anneals are shown to be detrimental to forming boron ultra shallow junctions.

Continuous and precise work function adjustment for integratable dual metal gate CMOS technology using Hf-Mo binary alloys

We demonstrate for the first time a continuous and almost linear work function adjustment between 3.93 and 4.93eV using Hf/sub x/Mo/sub (1-x)/ binary alloys deposited by co-sputtering. In view of the process integration, dual work function metal gate technology using Mo and Hf/sub x/Mo/sub (1-x)/ formed by metal intermixing was proposed. Work function values were verified to be a function of the thickness ratio and accurate work function adjustment can be possible. Furthermore, one can be allowed to get around the thermal stability issue by choosing an appropriate total metal thickness corresponding to the thermal budget subsequent to gate deposition, since the thermal budget required for metal intermixing depends on the total metal thickness.

A novel transient characterization technique to investigate trap properties in HfSiON gate dielectric MOSFETs-from single electron emission to PBTI recovery transient

A positive bias temperature instability (PBTI) recovery transient technique is presented to investigate trap properties in HfSiON as high-k gate dielectric in nMOSFETs. Both large- and small-area nMOSFETs are characterized. In a large-area device, the post-PBTI drain current exhibits a recovery transient and follows logarithmic time dependence. In a small-area device, individual trapped electron emission from HfSiON gate dielectric, which is manifested by a staircase-like drain current evolution with time, is observed during recovery. By measuring the temperature and gate voltage dependence of trapped electron emission times, the physical mechanism for PBTI recovery is developed. An analytical model based on thermally assisted tunneling can successfully reproduce measured transient characteristics. In addition, HfSiON trap properties, such as trap density and activation energy, are characterized by this method.

Novel dual-metal gate technology using Mo-MoSi/sub x/ combination

A novel dual-metal gate technology that uses a combination of Mo-MoSi/sub x/ gate electrodes is proposed. An amorphous-Si/Mo stack was fabricated as a gate electrode for the n-channel device. It was thermally annealed to form MoSi/sub x/. Pure Mo served as the gate electrode for the p-channel device. The work functions of MoSi/sub x/ and pure Mo gates on SiO/sub 2/ are 4.38 and 4.94 eV, respectively, which are appropriate for devices with advanced transistor structures. The small increase in the work function (< 20 meV) and the negligible equivalent oxide thickness variation (< 0.08 nm) after rapid thermal annealing at 950 /spl deg/C for 30 s also demonstrate the excellent thermal stabilities of Mo and MoSi/sub x/ on SiO/sub 2/. Additional arsenic ion implantation prior to silicidation was demonstrated further to lower the work function of MoSi/sub x/ to 4.07 eV. This approach for modulating the work function makes the proposed combination of Mo-MoSi/sub x/ gate electrodes appropriate for conventional bulk devices. The developed dual-metal-gate technology on HfO/sub 2/ gate dielectric was also evaluated. The effective work functions of pure Mo and undoped MoSi/sub x/ gates on HfO/sub 2/ are 4.89 and 4.34 eV, respectively. A considerable work-function shift was observed on the high-/spl kappa/ gate dielectric. The effect of arsenic preimplantation upon the work function of the metal silicide on HfO/sub 2/ was also demonstrated, even though the range of modulation was a little reduced.

Reliability of HfSiON as gate dielectric for advanced CMOS technology

Optimizing nitrogen incorporation in HfSiON gate dielectric can improve overall reliability, e.g. nMOS PBTI lifetime, hot carrier (HC) lifetime, time-to-breakdown (tBD), without adverse effects on pMOS NBT1 lifetime and electron/hole mobility. The improvement is attributed to excellent thermal stability against partial-crystallization after 1100/spl deg/C annealing, and the concomitantly reduced trap generation minimizes stress induced leakage current (SILC) and flicker noise degradation after PBTI stress. A new methodology is proposed, for the first time, to correctly predict HC lifetime of HfSiON nMOS based on electron trapping.

Hot carrier reliability improvement by utilizing phosphorus transient enhanced diffusion for input/output devices of deep submicron CMOS technology

This letter presents a deep submicron CMOS process that takes advantage of phosphorus transient enhanced diffusion (TED) to improve the hot carrier reliability of 3.3 V input/output transistors. Arsenic/phosphorus LDD nMOSFETs with and without TED are fabricated. The TED effects on a LDD junction profile, device substrate current and transconductance degradation are evaluated. Substantial substrate current reduction and hot carrier lifetime improvement for the input/output devices are attained due to a more graded n/sup -/ LDD doping profile by taking advantage of phosphorus TED.

Thermal stability of Hf/sub x/Ta/sub y/N metal gate electrodes for advanced MOS devices

In this letter, the composition effects of hafnium (Hf) and tantalum (Ta) in Hf/sub x/Ta/sub y/N metal gate on the thermal stability of MOS devices were investigated. The work function of the Hf/sub x/Ta/sub y/N metal gate can reach a value of /spl sim/4.6 eV (midgap of silicon) by suitably adjusting the Hf and Ta compositions. In addition, with a small amount of Hf incorporated into a TaN metal gate, excellent thermal stability of electrical properties, including the work function, the equivalent oxide thickness, interface trap density and defect generation rate characteristics, can be achieved after a post-metal anneal up to 950/spl deg/C for 45 s. Experimental results indicate that Ta-rich Hf/sub x/Ta/sub y/N is a promising metal gate for advanced MOS devices.

Characteristics and physical mechanisms of positive bias and temperature stress-induced drain current degradation in HfSiON nMOSFETs

Drain current degradation in HfSiON gate dielectric nMOSFETs by positive gate bias and temperature stress is investigated by using a fast transient measurement technique. The degradation exhibits two stages, featuring a different degradation rate and stress temperature dependence. The first-stage degradation is attributed to the charging of preexisting high-k dielectric traps and has a log(t) dependence on stress time, whereas the second-stage degradation is mainly caused by new high-k trap creation. The high-k trap growth rate is characterized by two techniques, namely 1) a recovery transient technique and 2) a charge-pumping technique. Finally, the effect of processing on high-k trap growth is evaluated.

Arsenic/phosphorus LDD optimization by taking advantage of phosphorus transient enhanced diffusion for high voltage input/output CMOS devices

Optimization of a LDD doping profile to enhance hot carrier resistance in 3.3 V input/output CMOS devices has been performed by utilizing phosphorus transient enhanced diffusion (TED). Hot carrier effects in hybrid arsenic/phosphorus LDD nMOSFETs with and without TED are characterized comprehensively. Our result shows that the substrate current in a nMOSFET with phosphorus TED can be substantially reduced, as compared to the one without TED. The reason is that the TED effect can yield a more graded n/sup -/ LDD doping profile and thus a smaller lateral electric field. Further improvement of hot carrier reliability can be achieved by optimizing arsenic implant energy. Secondary ion mass spectrometry analysis for TED effect and two-dimensional (2-D) device simulation for electric field and current flow distributions have been conducted. The phosphorus TED effects on transistor driving current and off-state leakage current are also investigated.

An atomic level study of multiple co-implantation technology for 32nm and beyond pMOSFETs ultra-shallow junction

Carbon, Fluorine, and Nitrogen are the co-implant species known for performing PMOS ultra-shallow junction. For the first time, it is demonstrated that the combination of the above three co-implant species could be most effective in suppressing boron diffusion for the continuous device performance improvement of sub-32nm technology. Vth roll-off characteristics were dramatically improved and a DIBL improvement of 30mV/V was demonstrated by applying this multiple co-implantation technology. Distinctive effect of each co-implant species for PMOS ultra-shallow junction formation was found and clarified for the first time based on SIMS analysis and kinetic Monte Carlo simulation.