Jack Y.-C. Sun

CMOS technology for MS/RF SoC

Accelerated scaling of CMOS technology has contributed to remove otherwise fundamental barriers preempting its widespread application to mixed-signal/radio-frequency (MS/RF) segments. Improvements in device speed, matching, and minimum noise figure are all consistent with fundamental scaling trends. Other figures-of-merit such as linearity and 1/f noise do not scale favorably but are not considered to be roadblocks when viewed from a circuit design perspective. Furthermore, interconnect architectural scaling trends in logic technology have facilitated improvements in passive-component performance metrics. These improvements compounded with innovations in circuit design have made CMOS technology the primary choice for cost driven MS/RF applications. This paper reviews active and passive elements of CMOS MS/RF system-on-chip (SoC) technology from a scaling perspective. The paper also discusses the implications that physical phenomena such as mechanical stress and gate leakage as well as gate patterning have on technology definition and characterization.

Characterization and comparison of high-k metal-insulator-metal (MiM) capacitors in 0.13 /spl mu/m Cu BEOL for mixed-mode and RF applications

In this paper, we report high-k MiM capacitors including Ta/sub 2/O/sub 5/, TaO/sub x/N/sub y/, HfO/sub 2/, Al/sub 2/O/sub 3/ and Ta/sub 2/O/sub 5//Al/sub 2/O/sub 3/ stack layer integrated in 0.13 /spl mu/m 8-level Cu-metallization technology using Cu barrier as both top and bottom electrodes. Ta/sub 2/O/sub 5/ exhibits excellent voltage and temperature linearity of capacitance. Al/sub 2/O/sub 3/ shows low leakage, but poor voltage and temperature linearity. Voltage linearity could be significantly affected by high-k deposition temperature. We present high-k MiM capacitors with voltage linearity as low as 25 ppm/V and 13 ppm/V/sup 2/.

Comprehensive Analysis of Short-Channel Effects in Ultrathin SOI MOSFETs

This paper analyzes the 2-D short-channel effect in ultrathin SOI MOSFETs. An empirical, channel length-dependent scale length is extracted from the lateral field slope of a series of numerically simulated devices. We show how this scale length is related to the short-channel threshold voltage roll-off and minimum channel length with and without a substrate bias. The benefit of a reverse substrate bias is investigated and understood in terms of the field and distribution of inversion charge in the silicon film. In particular, how a bulk-like short-channel effect is achieved when an accumulation layer is formed at the back surface. Furthermore, the effect of a high-κ gate insulator is studied and scaling implications discussed.

Advanced CMOS technology portfolio for RF IC applications

A high quality 90-nm CMOS-based technology portfolio suitable for various RF IC applications is presented. The portfolio is built up by a wide selection of active and passive components and a user-friendly process design kit (PDK). Layout-optimized RF components are studied in details including state-of-the-art 90 nm RFMOS devices with 120-160 GHz f/sub T/ and very low noise figures, varactors with tradeoff between quality factor and tuning ratio, precision capacitors with metal-insulator-metal and metal-over-metal schemes, and a variety of inductor structures suitable for different RF designs. The effectiveness for isolating substrate RF noise is also compared among several layout schemes. Finally the guidelines and requirements for constructing a useful PDK are addressed.

Improving the RF performance of 0.18 /spl mu/m CMOS with deep n-well implantation

The radio-frequency (RF) figures of merit of 0.18 /spl mu/m complementary metal-oxide-semiconductor (CMOS) technology are investigated by evaluating the unity-current-gain cutoff frequency (F/sub t/) and maximum oscillation frequency (F/sub max/). The device fabricated with an added deep n-well structure is shown to greatly enhance both the cutoff frequency and the maximum oscillation frequency, with negligible DC disturbance. Specifically, an 18% increase in F/sub t/ and 25% increase in F/sub max/ are achieved. Since the deep n-well implant can be easily adopted in a standard CMOS process, the approach appears to be very promising for future CMOS RF applications.

A 65nm node strained SOI technology with slim spacer

A 65 nm node strained SOI technology with high performance is demonstrated, providing drive currents of 1015 and 500 /spl mu/A//spl mu/m for N-FET and P-FET, respectively, at an off-state leakage of 40 nA//spl mu/m using 1 V operation. The technology employs an aggressively scaled slim spacer of 30 nm width to amplify stress benefits for performance improvement, and to reduce by 10-20 % the layout area for SRAM-cell-like circuits, while maintaining excellent hot carrier immunity and well-controlled short-channel effects. For the first time, we demonstrate that FinFET devices, implicitly implemented in this technology, offer a 8-15 % higher inverter speed compared to planar SOI devices at the same drive current.

Strained FIP-SOI (finFET/FD/PD-SOI) for sub-65 nm CMOS scaling

A highly manufacturable SOI technology with strained silicon and FinFET-like devices is demonstrated for sub-65 nm device scaling. This technology, named FIP-SOI (FinFET/FD/PD-SOI), achieves (1) performance gain of 10-35% for N-MOS using strained silicon compared with non-strained SOI, (2) bulk-to-SOI design portability without additional structures such as the body-contacted transistor scheme, and (3) superior scalability by the incorporation of FinFET-like devices. All feature size scaling (gate length, channel width, and SOI body thickness) will further enhance channel strain in the FIP-SOI. Scaling-strengthened strain is demonstrated for the first time.

Hot carrier reliability improvement by utilizing phosphorus transient enhanced diffusion for input/output devices of deep submicron CMOS technology

This letter presents a deep submicron CMOS process that takes advantage of phosphorus transient enhanced diffusion (TED) to improve the hot carrier reliability of 3.3 V input/output transistors. Arsenic/phosphorus LDD nMOSFETs with and without TED are fabricated. The TED effects on a LDD junction profile, device substrate current and transconductance degradation are evaluated. Substantial substrate current reduction and hot carrier lifetime improvement for the input/output devices are attained due to a more graded n/sup -/ LDD doping profile by taking advantage of phosphorus TED.

A 26 ps self-aligned epitaxial silicon base bipolar technology

A self-aligned epitaxial base technology is presented which allows fabrication of advanced bipolar devices with 40 to 60 nm basewidths and implementation of novel profile design concepts. The viability of this technology for advanced bipolar circuits has been examined by fabricating ECL ring oscillators, thus demonstrating that fully scaled epi-base devices can be successfully integrated. Devices with current gains of 80-90 and intrinsic base sheet resistances less than 10 kΩ/sq were fabricated. Epitaxial technology was used to position a novel lightly doped collector (LDC) spacer within the base collector junction of these heavily doped, thin-base devices to control avalanche breakdown and increase BVCEO. Conventional and active pull-down ECL ring oscillators with minimum gate delays of 40.5 and 26.3 ps, respectively, were fabricated with devices showing a measured cutoff frequency of 19.6 GHz

High-Performance PMOS Devices on (110)/ Substrate/Channel with Multiple Stressors

A study was performed to investigate the effect of multiple stressors on CMOS devices on (110) and (100) substrates with different channel directions. For the first time, 87% ION-IOFF improvement is achieved by utilizing SiGe-S/D and compressive contact etch stop layer (c-CESL) for PMOS devices on (110) substrate with lang111rang channel direction. The improvement is similar to that on conventional (100) substrate with lang110>rangchannel direction and can be explained by piezoresistive coefficients. Record PMOS device performance of Ion = 900 muA/mum at Ioff = 100 nA/mum and VDD = 1.0V for 40nm gate length is demonstrated