Hsichang Liu

An enhanced thermo-compression bonding process to address warpage in 3D integration of large die on organic substrates

In this work, a controlled thermo-compression (TC) bonding process has been developed to address problems caused by interposer and laminate warpage when assembling large three-dimensional (3D) integrated circuit (IC) die on an organic substrate (laminate). By using TC bonding, a thin interposer with through-silicon-vias (TSV) is joined to a top die while being held flat by vacuum and vertical pressure. A vacuum distribution plate is developed and used to mitigate warpage during 3D assembly. A unique set of process parameters has been developed which enables the joining of severely bowed, large area interposers to a semiconductor die without C4 (Controlled Collapse Chip Connection) shorting. The controlled TC bonding method developed in this work offers a huge advantage when joining multiple large warped die in a stack. This evaluation used a large 22 nm CMOS top die with ultra low-K (ULK) back end of the line (BEOL) and copper pillar/SnAg solder bumps at two different pitch sizes, 61 μm and 131 μm. Both the top die and interposer die were larger than 600 mm2 while the organic substrate was 68.5 mm × 68.5 mm. The top die and interposer were bonded with parameters developed for an enhanced TC bonding process. Cross-sectional analysis of the 3D assembly showed that the solder joints along the perimeter of chips exhibited good joining with good solder wettability and no solder bridging. Non-destructive X-ray analysis also confirmed that there were no C4 bump bridging across the entire chip area. The experimental results verified that the enhanced TC bonding process can effectively prevent C4 bump bridging and C4 bump electrical opens for a large die packaged in a 3D configuration with a highly warped large area silicon interposer.

An efficient lid design for cooling stacked flip-chip 3D packages

3D chip-stack packages are more difficult to cool than 2D chip packages due to additional thermal resistances in the heat flow path. The additional thermal resistances are due to the presence of the C4 joins between the chips, the BEOL wiring layers in each chip and the silicon thickness of the chips in the stack. In this paper we present an efficient lid design for a 3D flip-chip package that allows contact, through a thin thermal interface material (TIM) layer, of exposed chip regions of the lower chips in the 3D vertical stack. The efficient lid was assembled on to 3D thermal test vehicle packages and its thermal advantage over standard lid 3D packages was experimentally demonstrated. The packages were cross-sectioned to ensure that the assembly process yielded the correct TIM gaps. A thermal conduction model was calibrated to the experimental data and the stacked chip-chip and the efficient lid TIM thermal resistances were extracted from the model. A sensitivity analysis was then conducted to identify the important parameters controlling the thermal performance of the 3D package.

Bonding technologies for chip level and wafer level 3D integration

This paper provides a comparison of bonding process technologies for chip and wafer level 3D integration (3Di). We discuss bonding methods and comparison of the reflow furnace, thermo-compression, Cavity ALignment Method (CALM) for chip level bonding, and oxide bonding for 300 mm wafer level 3Di. For chip 3Di, challenges related to maintaining thin die and laminate co-planarity were overcome. Stacking of large thin Si die with 22 nm CMOS devices was achieved. The size of the die was more than 600 mm2. Also, 300 mm 3Di wafer stacking with 45 nm CMOS devices was demonstrated. Wafers thinned to 10 μm with Cu through-silicon-via (TSV) interconnections were formed after bonding to another device wafer. In either chip or wafer level 3Di, testing results show no loss of integrity due to the bonding technologies.

Development of a Low CTE chip scale package

This paper describes the development of a low CTE organic Chip Scale Package (CSP) jointly by KST and IBM. Tests carried out on the low CTE laminate material and subsequently on the related CSP are described. The new material set, identified as Advanced SLC Package, combines low CTE core and build-up dielectric materials to achieve a composite laminate CTE of 9-12 ppm/°C, which is intermediate between the CTEs of silicon device and conventional board. The lower composite CTE reduces the dimensional mismatch between chip and laminate during Bond and Assembly (BA) to mitigate Chip-Package Interactions (CPI) and white bumps. The low CTE significantly reduces the strain in the solder joints during the reflow process and ensures the solder joint reliability. Global and chip-site warp data from thermo-mechanical modeling are compared to the measured warp data. In addition, other mechanical risk factors for a CSP during BA and reliability stress conditions are evaluated.

Delamination mechanisms of thermal interface materials in organic packages during reflow and moisture soaking

A thermal interface material (TIM) is typically a compliant material with high thermal conductivity that is applied between a heat-generating chip and a heat spreader in an electronic package. For a high-conductivity polymeric TIM, the adhesion strength between the TIM and its mating interfaces is typically weak, making the TIM susceptible to degradation when subjected to environmental stresses. At typical chip operating temperatures which are below the curing temperature of the TIM, a compressive force acts on the TIM at the chip center due to the CTE mismatch between the die and the organic chip carrier. Conversely at high BGA(Ball Grid Array) or card-attach reflow temperatures, the TIM center is under tension and the TIM tends to either cohesively separate or adhesively separate from the interfaces. Also, during moisture soaking, such as 85C/85%RH, the organic chip carrier absorbs moisture and expands. The hygroscopic expansion of the organic chip carrier is of the same order of magnitude as the thermal expansion. This expansion reduces the compressive force acting on the TIM, and for certain package constructions, this can lead to degradation of thermal performance. In this paper, the delamination mechanism of a polymer-based thermal interface material in an organic package during reflow and moisture soaking is investigated. The in-situ deformation of the TIM bondline was measured by a digital image correlation (DIC) method on a cross-sectioned part. The TIM bondline deformation was also captured by a digital camera. The coefficients of thermal expansion and hygroscopic expansion for different organic materials were measured, and a finite element analysis of the hygroscopic expansion and TIM bondline deformation was conducted. The affect of T&H stress was analyzed using an equivalent CTE concept.

Multi-chip package thermal management of IBM z-server systems

The recently announced IBM z9 server system presents unique cooling requirements from a packaging perspective. Cooling has to be achieved for sixteen chips mounted on a common glass ceramic chip carrier. Eight of the sixteen chips dissipate significant power. A recently described small gap technology (SGT) is used to attain customized chip to cap gaps. An advanced thermal compound (ATC) is used as the interface between the chips and the cap. The package thermal and mechanical design is first described. Design optimization is achieved by detailed finite element thermo-mechanical modeling. The complex encapsulation process to attain the correct chip to hat ATC gaps is outlined. Verification of the ATC gaps is an integral part of the assembly process. The reliability qualification is then discussed. Issues found during the qualification were the structural fragility of the glass ceramic chip carrier flange and ATC thermal degradation. The structural robustness of the chip carrier was improved by modifying its design. ATC degradation is quantitatively related to the shear strain

Failure analysis of thermal degradation of TIM during power cycling

This paper discusses a thermal reliability testing experiment and failure analysis (FA) in 32nm SOI Si technology chip packages. Thermal performance of the TIM materials is monitored and physical failure analysis is performed on test vehicle packages post thermal reliability test. Thermomechanical modeling is conducted for different test conditions. TIM thermal degradation is observed at the chip center area in the batch of samples post power cycling (PC) test, while the TIM performance remains normal in the other batch of samples post thermal aging (TA) test. Physical FA findings after TIM bond line thickness measurement (at the chip corners and chip center) and unlidding to inspect the TIM surface morphology confirmed the failure mode is TIM to chip tearing. Finite element modeling results indicate significant difference of stress status in TIM and sealband adhesive between PC and TA test. The TIM experiences compressive stress during PC test, while it is in tensile stress during TA test.

Nondestructive Measurement of C4 BLM Undercut by Scanning Acoustic Microscope

A non-destructive measurement of ball limiting metallurgy (BLM) undercut is demonstrated by using C-mode scanning acoustic microscopy. The results from CSAM measurements agree well with the optical and cross-section data. The implementation of the method in manufacturing will not only save time and cost on destructive failure analysis such as cross section and chemical un-layering, but also provide a way for monitoring process trend for early detection and correction of process abnormalities.Copyright