Hsien-Ku Chen

The origin of the kink phenomenon of transistor scattering parameter S/sub 22/

A novel theory based on dual-feedback circuit methodology is proposed to explain the kink phenomenon of transistor scattering parameter S/sub 22/. Our results show that the output impedance of all transistors intrinsically shows a series RC circuit at low frequencies and a parallel RC circuit at high frequencies. It is this inherent ambivalent characteristic of the output impedance that causes the appearance of kink phenomenon of S/sub 22/ in a Smith chart. It was found that an increase of transistor transconductance enhances the kink effect while an increase of drain-to-source (or collector-to-emitter) capacitance obscures it. This explains why it is much easier to see the kink phenomenon in bipolar transistors, especially heterojunction bipolar transistors, rather than in field-effect transistors (FETs). It also explains why the kink phenomenon is seen in larger size FETs and not in smaller size FETs. Our model not only can predict the behavior of S/sub 22/, but also calculate all S-parameters accurately. Experimental data of submicrometer gate Si MOSFETs and GaAs FETs are used to verify our theory. A simple method for extracting transistor equivalent-circuit parameters from measured S-parameters is also proposed based on our theory. Compared with traditional Z- or Y-parameter methods, our theory shows another advantage of giving deep insight into the physical meaning of S-parameters.

Analysis and Design of a 1.6–28-GHz Compact Wideband LNA in 90-nm CMOS Using a

This paper presents a wideband low-noise amplifier (LNA) based on the cascode configuration with resistive feedback. Wideband input-impedance matching was achieved using a shunt-shunt feedback resistor in conjunction with a preceding π -match network, while the wideband gain response was obtained using a post-cascode inductor (LP), which was inserted between the output of the cascoding transistor and the input of the shunt-shunt resistive feedback network to enhance the gain and suppress noise. Theoretical analysis shows that the frequency response of the power gain, as well as the noise figure (NF), can be described by second-order functions with quality factors or damping ratios as parameters. Implemented in 90-nm CMOS technology, the die area of this wideband LNA is only 0.139 mm2 including testing pads. It dissipates 21.6-mW power and achieves S11 below -10 dB, S22 below -10 dB, flat S21 of 9.6 ±1.1 dB, and flat NF of 3.68 ± 0.72 dB over the 1.6-28-GHz band. Besides, excellent input third-order inter-modulation point of +4 dBm is also achieved. The analytical, simulated, and measured results are mutually consistent.

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A wideband low-noise amplifier (LNA) with shunt resistive-feedback and series inductive-peaking is proposed for wideband input matching, broadband power gain and flat noise figure (NF) response. The proposed wideband LNA is implemented in 0.18-mum CMOS technology. Measured results show that power gain is greater than 10 dB and input return loss is below -10 dB from 2 to 11.5 GHz. The IIP3 is about +3 dBm, and the NF ranges from 3.1 to 4.1 dB over the band of interest. An excellent agreement between the simulated and measured results is found and attributed to less number of passive components needed in this circuit compared with previous designs. Besides, the ratio of figure-of- merit to chip size is as high as 190 (mW-1 /mm2 ) which is the best results among all previous reported CMOS-based wideband LNA.

-Match Input Network

In this paper, we have developed an interpretation of transistor S-parameters by poles and zeros. The results from our proposed method agreed well with experimental data from GaAs FETs and Si MOSFETs. The concept of source-series feedback was employed to analyze a transistor circuit set up for the measurement of the S-parameters. Our method can describe the frequency responses of all transistor S-parameters very easily and the calculated S-parameters are scalable with device sizes. It was also found that the long-puzzled kink phenomenon of S/sub 22/ observed in a Smith chart can be explained by the poles and zeros of S/sub 22/.

A Compact Wideband CMOS Low-Noise Amplifier Using Shunt Resistive-Feedback and Series Inductive-Peaking Techniques

This paper presents two voltage controlled oscillators (VCOs) operating at 5.42 and 5.76 GHz implemented in 0.18-μm complementary metal-oxide semiconductor (CMOS) technology with integrated passive device (IPD) inductors. One IPD inductor was stacked on the top of the active region of the 5.76-GHz VCO chip, whereas the other IPD inductor was placed on the top of the 5.42-GHz VCO CMOS chip but far from the its active region. The high-quality IPD inductors reduce the phase noise of the VCOs. The measurements of the two VCOs indicate the same phase noise of -120 dBc/Hz at 1 MHz offset frequency. These results demonstrate a 6-dB improvement compared to the VCO using an on-chip inductor. This paper also presents the effect of the coupling between the IPD inductor and the active region of the chip on the phase noise performance.

A novel interpretation of transistor S-parameters by poles and zeros for RF IC circuit design

An intrinsic-tuned, 68 GHz voltage controlled oscillator (VCO) without an extra on-chip accumulation-mode metal oxide semiconductor (MOS)-varactor is demonstrated in a standard, 0.13 mum CMOS technology. This VCO exhibits phase noises of -98.4 dBc/Hz and -115.2 dBc/Hz at 1 and 10 MHz offset, respectively, along with a tuning range of 4.5 % even under a small power consumption of 4.32 mW. Besides, the highest figure-of-merit (taking frequency tuning range into account) of -182 dBc/Hz under the 1 MHz offset condition is achieved among all previously reported >60 GHz CMOS-based VCOs, which is attributed to the proposed intrinsic tuning mechanism.

Low Phase Noise and Low Power Consumption VCOs Using CMOS and IPD Technologies

The availability of unlicensed mm-wave bands has fueled the research and development of mm-wave wireless systems. If different frequency bands can be operated from one signal source, it will reduce the circuit size and power consumption, leading to compact systems. For example, the frequencies 38, 57, 76GHz in 38, 60 and 77GHz bands can be generated by using only one PLL, as illustrated in Fig. 16.4.1. To address this requirement, in this paper, a multiband multimode injection-locked frequency divider (M-ILFD) is presented that meets the requirements for 38 and 57GHz applications.

A 0.6 V, 4.32 mW, 68 GHz Low Phase-Noise VCO With Intrinsic-Tuned Technique in 0.13

A 30-GHz wide locking-range (25%) injection-locked frequency divider (ILFD) with small power consumption (1.86 mW) is presented. The locking range of the ILFD is extended by reducing the quality factor of resonant tank. Besides, the output power level of second harmonic is lower than that of fundamental component by 37 dBc due to the new output buffer where the second harmonic can be cancelled. The proposed wideband ILFD is implemented in 0.13-mum standard CMOS process. It achieves a wide locking-range of 6.2 GHz (25 %) without any frequency tuning mechanism under the small power consumption of 1.86 mW and the highest figure-of-merit of 12.4 (%/mW) among all reported state-of-the-art CMOS ILFD.

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A complete CMOS wideband low noise amplifier (LNA) has been designed with off-chip passive device. The input inductor with integrated passive device (IPD) is used for input matching and NF improvement due to its high quality factor (Q). The large inductance of 4.7 nH of choke is used for covering the bandwidth of 2∼11 GHz, which is stacked on the top of CMOS for chip-area saving. Besides, the interaction between CMOS and IPD for passive devices is also considered in the work. The CMOS wideband LNA is with the merits of cost-effective and high-performance compared to the pure CMOS circuit.

m CMOS

A 9-GHz quadrature voltage-controlled oscillator (QVCO) with an improvement of 1/f noise performance due to the use of proposed source-follower coupling technique is presented. In contrast to conventional parallel or series coupling methods by which the coupling transistors are operated in saturation region, the source-follower coupling technique, which uses a coupling transistor operated in cut-off region, is invented. Therefore, 1/f noise is much lower than that of the conventional topologies due to the less turn-on duty cycle of the coupling-transistor than that of conventional one, which in turns results in smaller phase noise. It is found experimentally that the phase noise of the QVCO can be reduced by more than 8 dB due to the suppression the 1/f noise of coupling transistor by changing its operation condition from saturation to cut-off region. This QVCO achieves a phase noise of -115 dBc/Hz at 1-MHz-offset away from the 9.17 GHz carrier, corresponding to a figure-of-merit (FOM) of -183.4 dBc/Hz.