Huajie Zhou

High-Performance Silicon Nanowire Gate-All-Around nMOSFETs Fabricated on Bulk Substrate Using CMOS-Compatible Process

In this letter, a novel self-aligned CMOS-compatible method for the fabrication of gate-all-around silicon nanowire MOSFETs (GAA SNWFETs) on bulk substrate has been proposed. The fabricated SNWFET featuring 33-nm gate length and 7-nm diameter shows the highest driving current (<i>I</i>_on = 2500 μA/μm at <i>V</i>_ds = <i>V</i>_gs = 1.0 V) among previously reported data and achieves high <i>I</i>_on/<i>I</i>_off ratio of 10⁵, lightening the promise for high performance and strong scalability of GAA SNWFETs. The process details and optimization procedure are extensively discussed.

Performance Breakthrough in Gate-All-Around Nanowire n- and p-Type MOSFETs Fabricated on Bulk Silicon Substrate

We demonstrate high-performance silicon-nanowire gate-all-around MOSFETs (GAA SNWFETs) fabricated on bulk Si by a novel top-down complementary MOS-compatible method. The fabricated nand p-type GAA SNWFETs of ~50-nm gate length and of ~6-nm diameter show superior device performance, i.e., driving capability of 2.6 × 10³/2.9 × 10³ μA/μm at |V_D| = |V_G - V_t| = 1.0 V, I_on/I_off ratio as high as 5 × 10⁸/10⁹, and excellent short-channel-effect immunity with subthreshold slope of 67/64 mV/dec and drain-induced barrier lowering of 6 mV/V, respectively. GAA SNWFETs and FinFETs fabricated on bulk Si were also compared by the investigation of both experiments and Technology Computer Aided Design simulation. The superiority of GAA SNWFETs over FinFETs is evidenced in this paper.

Design and optimization considerations for bulk gate-all-around nanowire MOSFETs

In this paper, design and optimization considerations for bulk gate-all-around nanowire MOSFETs have been investigated based on calibrated three-dimensional quantum correction numerical simulation. As device parasitical parameters play a crucial role in the optimization of overall performance of nanoscale bulk nanowire MOSFETs, we have placed great emphasis on projecting insights into the design of parasitic grooved-gate transistor and the source/drain (S/D) extension region. Furthermore, taking several important electrical parameters such as Vth, Ion, Ioff, subthreshold swing (Ss) and drain-induced barrier lowering (DIBL) as scaling criteria, the scaling of gate dielectric oxide (tox) and the diameter of nanowire (tsi) is discussed. The request for a high-k gate dielectric could be postponed due to the novel advanced structure, and there exists an optimal tsi for high performance application.

Ion-Implanted TiN Metal Gate With Dual Band-Edge Work Function and Excellent Reliability for Advanced CMOS Device Applications

This paper proposed, for the first time, that the dual band-edge effective work functions are achieved by employing a single metal gate (MG) and single high-k (HK) dielectric via ion implantation into a TiN MG for HP CMOS device applications under a gate-last process flow. The P/BF2 ion-implanted TiN/HfO2/ILSiO2 gate-stack does not degrade the gate leakage, reliability, and carrier mobility, and reduces the effective oxide thickness. The impact of P/BF2 ion implant energy, dose, and TiN gate thickness on the properties of implanted TiN/HfO2/ILSiO2 gate-stack is studied, and the corresponding possible mechanisms are discussed. This technique has been successfully applied to the replacement MG and HK/MG last process flow to fabricate HP CMOSFETs and CMOS 32 frequency dividers with a minimum gate length of 25 nm.

Investigation of Key Technologies for Poly-Si/TaN/HfLaON/IL

We demonstrated for the first time integration of a poly-Si/TaN/HfLaON/IL SiO₂ gate-stacks into high-performance sub-30-nm nMOSFETs using a gate-first process flow successfully. The properties of TaN/HfLaON/IL SiO₂ gate-stacks were studied. The results showed that the HfLaON gate dielectric material exhibited excellent thermal stability and electrical characteristics. A three-step dry etching method used to etch poly-Si/TaN/HfLaON/IL SiO₂ gate-stack was proposed to provide an effective pathway for patterning the complex gate-stacks. At V_DS=V_GS=0.9 V, the drive current I_ON of 410 μA/μm was achieved at an OFF-state leakage current I_OFF of 180 nA/μm. The threshold voltage of saturation extracted at I_DS of 3 μA/μm was 0.14 V. The subthreshold slope of 92 mV/decade and drain induced barrier lowering of 93 mV/V were obtained.

{\rm SiO}_{2}

HfSiON gate dielectric with equivalent oxide thickness of 10Å was prepared by reactive sputtering. It exhibits good physical and electrical characteristics, including good thermal stability up to 900°C, high dielectric constant and low gate leakage current. It was integrated with TaN metal gate in a novel gate-last process flow to fabricate NMOSFET. In the process, poly-silicon was deposited on HfSiON gate dielectric as dummy gate and replaced by TaN metal gate after source/drain formation. Because of the metal gate formation after the ion-implant doping activation at high temperature, HfSiON/TaN NMOSFET with good driving ability and excellent sub-threshold characteristics was fabricated.

Gate-Stacks in Advanced Device Applications

We demonstrate high performance silicon nanowire gate-all-around MOSFETs (SNWFETs) fabricated on bulk Si by a novel top-down CMOS-compatible method. The fabricated N- and P-type SNWFETs of sub-50 nm gate length and of ∼5 nm in diameter show excellent short channel effects (SCEs) immunity with subthreshold slope (SS) of 90/69 mV/dec, DIBL of 47/10 mV/V, and high driving current of 2×10³/5.4×10³ µA/µm at 0.1 nA/µm off-current.