Qingqing Liang

Performance Breakthrough in Gate-All-Around Nanowire n- and p-Type MOSFETs Fabricated on Bulk Silicon Substrate

We demonstrate high-performance silicon-nanowire gate-all-around MOSFETs (GAA SNWFETs) fabricated on bulk Si by a novel top-down complementary MOS-compatible method. The fabricated nand p-type GAA SNWFETs of ~50-nm gate length and of ~6-nm diameter show superior device performance, i.e., driving capability of 2.6 × 10³/2.9 × 10³ μA/μm at |V_D| = |V_G - V_t| = 1.0 V, I_on/I_off ratio as high as 5 × 10⁸/10⁹, and excellent short-channel-effect immunity with subthreshold slope of 67/64 mV/dec and drain-induced barrier lowering of 6 mV/V, respectively. GAA SNWFETs and FinFETs fabricated on bulk Si were also compared by the investigation of both experiments and Technology Computer Aided Design simulation. The superiority of GAA SNWFETs over FinFETs is evidenced in this paper.

Two-terminal vertical memory cell for cross-point static random access memory applications

In this work, the authors propose a 4F2 (F is the length of half pitch) memory cell with a vertical PNPN structure (silicon device with 4 layers doped with p-type, n-type, p-type and n-type dopants, respectively) to increase static random access memory (SRAM) integration density compared to the traditional 6T SRAM cell with an area of 90 ∼ 150F2. Thanks to the simple two-terminal configuration, the cross-point structure with proposed cell can be used in memory design, to achieve the highest density in planar complementary metal oxide semiconductor (CMOS) technology and to be implemented potentially in future three-dimensional integration. Experimental results demonstrate that the fabrication of proposed memory cell is compatible with CMOS process, little impact by process variation and reliability issues. Calibrated simulations display that the proposed cell can be programmed at nanosecond level speed with acceptable power consumption in most memory applications.

Gallium-Incorporated TiN Metal Gate With Band-Edge Work Function and Excellent Thermal Stability for PMOS Device Applications

A cost-effective method for modulating the effective work function (EWF) of a metal gate while simultaneously decreasing the equivalent oxide thickness (EOT) of a high-k dielectric is proposed for the first time. By incorporating gallium (Ga) into the TiN/HfLaON/interfacial layer (IL) SiO2 PMOS gate stack, a band-edge EWF of 5.18 eV and an EOT of 0.57 nm can be obtained. Excellent thermal stability was maintained even after the post metal anneal (PMA) at 1000°C. The impacts of TiN thickness, Ga implant doses, and PMA conditions on the properties of the Ga-incorporated TiN/HLaON/IL SiO2 gate stack are investigated, and the corresponding possible mechanisms are discussed. This technique has been successfully applied to the gate-first process flow to fabricate PMOSFETs with a minimum gate length of 28 nm.

Planar Bulk MOSFETs With Self-Aligned Pocket Well to Improve Short-Channel Effects and Enhance Device Performance

We present and demonstrate a self-aligned pocket well (SPW) structure used in planar bulk MOSFETs with a metal gate length of 25 nm and an effective channel length less than 20 nm. The SPW features a retrograde doping profile in vertical direction and a doping profile self-aligned with drain/extension in lateral direction. A novel process, called replacement spacer gate (RSG), is designed to avoid challenges in gate patterning and high-k metal gate filling. Planar bulk pMOSFETs, with SPW and halo doping, respectively, were simulated and fabricated adopting the RSG process. Due to its retrograde feature, the SPW can achieve low drain-induced barrier lowering (DIBL) along with low VT. Compared with halo doping with the same VT,sat at VDD = 0.8 V, despite no ION enhancement, the SPW reduces DIBL by 45% and enhances IEFF by 18%. Compared with halo doping with the same IOFF = 100 nA/μm at VDD = 0.8 V, the SPW structure reduces DIBL by 16%, enhances ION by 5%, and improves IEFF by 30%. In addition, with the self-aligned feature, the SPW does not deteriorate junction band-to-band tunneling (BTBT)

On the Control of Short-Channel Effect for MOSFETs With Reverse Halo Implantation

Reverse halo implantation (RHI), for the first time, is introduced and used to fabricate MOSFETs. It was demonstrated that RHI can dramatically improve short-channel effect, which can be used to enhance MOSFET performance, improve process control, or reduce stand-by power consumption. Implantation damage of RHI to gate oxide is negligible. The method of RHI is economic and suitable for massive manufacturing of very large scale integration

Ion-Implanted TiN Metal Gate With Dual Band-Edge Work Function and Excellent Reliability for Advanced CMOS Device Applications

This paper proposed, for the first time, that the dual band-edge effective work functions are achieved by employing a single metal gate (MG) and single high-k (HK) dielectric via ion implantation into a TiN MG for HP CMOS device applications under a gate-last process flow. The P/BF2 ion-implanted TiN/HfO2/ILSiO2 gate-stack does not degrade the gate leakage, reliability, and carrier mobility, and reduces the effective oxide thickness. The impact of P/BF2 ion implant energy, dose, and TiN gate thickness on the properties of implanted TiN/HfO2/ILSiO2 gate-stack is studied, and the corresponding possible mechanisms are discussed. This technique has been successfully applied to the replacement MG and HK/MG last process flow to fabricate HP CMOSFETs and CMOS 32 frequency dividers with a minimum gate length of 25 nm.

Simple approach for statistical modeling of process impacts on CMOS device variations in VLSI applications

A novel methodology to statistically analyze the statistics on small device performance is presented for the first time. To verify the accuracy of analysis and modeling, TCAD simulation is used to mimic possible process-induced and random fluctuations. The proposed approach precisely decouples various process dependency of the device electric behavior and predicts the device performance trend induced by these variables.

Interfacial Elastic Dipoles: A New EOT Shifting Mechanism in HKMG Devices

A new effective-oxide-thickness (EOT) shifting mechanism caused by the interfacial elastic dipoles is analyzed. The EOT can shift without changing the physical thickness of each dielectric layer. This phenomenon is first observed in the experiments of high-k metal-gate device optimization. Detailed studies and ab initio simulations show that this dipole-EOT correlation generally exists in any dielectric interfaces and should be carefully scrutinized in process development.

A new EOT shrinking mechanism in TiN/HfLaON HKMG MOSFET: Experimental and ab-initio study

Dramatic EOT shrinking and Vfb increasing were observed when implanting Ga ions into high-k/metal-gate stack. Experiments with different gate-metal thickness, dosages, ion types, and post gate-etch anneal conditions were studied. Elastic dipole theory, for the first time, is proposed and ab-initio simulations were conducted to explain the unexpected trends. This theory offers a good guide to choose plug-in materials for high-k/metal-gate optimization.

Simulations of FDSOI CMOS with Sharing Contact between Source/Drain and Back Gate

In this paper, a new ultra-thin fully-depleted SOI CMOS structure with sharing contact between source/drain and back gate is presented to save area and increase threshold voltage tuning capability. TCAD simulations are used to investigate the back-gate effect on the ultra-thin SOI CMOS. A new process flow to make the fully-depleted SOI CMOS structures is also proposed.