Sangeun Lee

A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS

This paper describes a low-power 100 Gigabit Ethernet transceiver IC compliant with IEEE802.3ba 100GBASE-LR4 in 40 nm CMOS. The proposed bidirectional full-duplex transceiver IC contains a total of eight 28 Gb/s CDRs. Each CDR lane incorporates phase-rotator-based delay- and phase-locked loop (D/PLL) architecture for enhanced jitter filtering. All the CDR lanes operate independently while sharing a single voltage-controlled oscillator and supporting referenceless clock acquisition. To reduce power consumption, a multidrop clock distribution scheme with single on-chip transmission-line (T-line) and quadrate RX and TX schemes without CML logic gates are incorporated. Embedded built-in self-test modules featuring a random accumulation jitter generator enables bit error rate (BER) and jitter tolerance self tests without any external equipment. The TX featuring a three-tap pre-emphasis provides a variable output swing ranging from 478 mVppd to 1.06 Vppd. RX equalizers employing a continuous-time linear equalizer and a one-tap decision feedback equalizer compensate for the channel loss up to 25 dB at the Nyquist rate. The measured RX input sensitivity for a BER of 10 -12 is 42 mVppd. The proposed IC consumes only 0.87 W at 28.0 Gb/s with a BER less than 10 -15 on PRBS31 testing. The power efficiency of the proposed transceiver is 3.9 mW/Gb/s, which is the best among the efficiencies achieved by recently published 25 Gb/s transceivers.

Investigating the Vulnerability of Dry-Season Water Supplies to Climate Change: A Case Study of the Gwangdong Reservoir Drought Management System, Korea

This study aims to improve the method to measure the vulnerability of water supply that arises mainly due to water scarcity in the dry season, and a situation that is expected to be exacerbated by climate change. The authors discuss the usefulness of the Gwangdong Reservoir Drought Management Model (GRDM2), which was developed in a previous study, and built on the basis of the adaptation mechanism, specifying the relationship between external disturbances (or future scenarios), system components pertaining to adaptation capacity, and vulnerability. The authors derive a total of 48 future scenarios, which consist of combinations of 6 future inflow scenarios and 8 future water requirement scenarios, of the Gwangdong reservoir drought management system. They then estimate the damage cost due to water scarcity in the dry season until the 2050s after feeding data in each scenario into GRDM2. The simulation reveals that extensive damage due to water scarcity may occur from the 2020s, and catastrophes, with damage four times greater than in the 2009 water scarcity accident, may occur in the 2050s. Assembling those results together, the authors conclude that GRDM2 is useful to measure the magnitude of climate change vulnerability, focusing on damage caused by water scarcity during the dry season. It is finally stated that to well prepare for climate change, engineers should investigate a suitable combination of available solutions, and at the same time perceive the threats that are attributed to high uncertainty.

Lessons from water scarcity of the 2008-2009 Gwangdong reservoir: needs to address drought management with the adaptiveness concept

Numerous publications document increasing consensus in the scientific community that climate change will increase the severity and frequency of drought. However, constructing large infrastructures is often viewed as an unreliable and inefficient option in dealing with the problem of drought, owing to unpredictability of climate change. This study aims at illustratively presenting that there is much room to improve drought management without resorting solely to infrastructure options. The adaptiveness concept is first explained to examine the reasons of failure in drought management and appropriate options from the viewpoint of a systems approach. Thereafter, a Korean water scarcity case is defined as the system dynamics model. The model is implemented to include movement of water via the reservoir and water supply facilities, the operating rules of the reservoir, and the relation between water scarcity and customer stress. Simulation results demonstrate that adaptiveness of drought management was low because of untimely or limited options of the reservoir operator. They also show that most customer stress could be largely mitigated by two options chosen from the adaptiveness concept. It is finally concluded that drought management needs to be addressed with consideration of the adaptiveness concept before deciding solely on expansion of infrastructure upon facing challenges due to climate change.

A 28-Gb/s Receiver With Self-contained Adaptive Equalization and Sampling Point Control Using Stochastic Sigma-Tracking Eye-Opening Monitor

This paper describes a 28-Gb/s receiver IC with self-contained adaptive equalization and sampling point control using an on-chip stochastic sigma-tracking eye-opening monitor (SSEOM). The proposed SSEOM accurately detects the bit-error-rate (BER)-related eye contour efficiently without the use of an external microcontroller. The SSEOM determines the BER-optimal sampling point and equalizer coefficients on the basis of pattern-filtered eye diagrams. It also features a background adaptation scheme for robust long-term operation by tracking temperature variations and device aging. The proposed SSEOM is integrated in a 28-Gb/s receiver that is designed to compensate for channel loss up to 25 dB at the Nyquist rate by using a continuous time linear equalizer (CTLE) and a one-tap decision feedback equalizer (DFE) together with an one-tap pre-emphasis at a transmitter. The time required for complete adaptation and the total power consumption are 364 ms and 43.9 mW, respectively. The proposed 28-Gb/s receiver is fabricated in 40 nm CMOS.

An Automatic Loop Gain Control Algorithm for Bang-Bang CDRs

An automatic loop gain control algorithm (ALGC) for a bang-bang (BB) clock and data recovery (CDR) is proposed. The proposed algorithm finds the optimum loop gain using the autocorrelation of a BBPD output signal for minimum MSE performance. Mathematical proof of the algorithm is presented for both rotator-based and VCO-based CDRs with finite loop delay. A 25 Gb/s transceiver IC is fabricated using a 40 nm CMOS process to validate the performance of the algorithm. The power consumptions of TX and RX are 37.8 mW and 46.8 mW, respectively and the synthesized area implementing a digital loop filter together with the proposed ALGC occupies 140 μm × 170 μm.

High-power Nd3+:glass laser system in KAIST (Sinmyung I)

A high-power Nd 3+ : glass laser system has been constructed and tested. This system consists of a master oscillator, a four-pass amplifier for preamplification, and five-stage amplifiers. The system has been demonstrated in excess of 80 J (2 TW) at 40-ps pulse duration. Final laser beam quality was quite good due to the compensation of the polarization distortion in the four-pass preamplifier, the minimization of the diffraction effect by the image relaying, and the elimination of high spatial frequency components by the spatial filtering. This enables us to obtain high laser output power without any severe spatial spiking effects. Gains and spatial profiles of output pulses were measured after each amplifier stage.

A 100-GbE reverse gearbox IC in 40nm CMOS for supporting legacy 10- and 40-GbE standards

This paper presents the industrys first low-power 100-Gigabit Ethernet (GbE) multi-link gearbox (MLG) IC, which facilitates transport of independent 10-GbE and 40-GbE signals to 4×25G physical layers implementing 100GBASE-R. The IC consumes only 1.37-W while implementing complicated reverse gearbox functionality. The measured TX jitter from the 25-Gb/s lane is 1.6-psrms, and the recovered clock jitter is 0.5-psrms. The measured RX input sensitivity for a BER 10-12 is 42-mVppd. The proposed gearbox IC, fabricated in a 40nm CMOS process, occupies 3.7×3.4-mm2. The power consumption of RX and TX in 25G interfaces are 47-mW and 51-mW, respectively, and those of a 10G interfaces are 24-mW and 25-mW, respectively. Gearbox functionalities are verified with embedded self-test logics.

A Power-and-Area Efficient

A phase interpolator (PI)-based 10 × 10 Gb/s bootstrap transceiver for referenceless and lane-independent operation is presented. PI output clock signals phase locked to the input data are used as reference clock signals for frequency locking the voltage-controlled oscillator (VCO). The VCO clock signal is then redistributed to the PIs, triggering the bootstrapping between the VCO and the PIs. All lanes operate independently as in VCO-based parallel referenceless designs while saving power and area. The measured recovered-data jitter in each lane is 0.93 psrms and the transceiver passes the OC-192 jitter-tolerance specification. A flip-chip packaged test chip is fabricated in a 40 nm CMOS technology. The test chip achieves figure-of-merits (mW/Gbps) of 2.03 and 2.13 for the receiver and the transmitter, respectively.

10\times 10

AbstractA genetic algorithm (GA) was combined with artificial neural networks (ANN), designated as neuro-genetic algorithm (NGA) in this study, to determine the effective number of nodes and optimal activated functions (FAs) in an ANN structure. Developed NGA was applied to predict Chlorophyll-a (Chl-a) concentrations in one-month increments in Lakes used as drinking water sources. Correlation analysis was used to setup input parameters. A simulation was conducted for four study sites with the most serious Chl-a problems in South Korea. Results from correlation analysis have indicated that phosphate phosphorus (PO4-P) and electrical conductivity showed high correlation with Chl-a, a factor not often considered in other studies. As the results of prediction of one-month forward Chl-a concentration, NGA showed high accuracy, with averaged determination coefficients of 0.89 and 0.84 in training and testing period, respectively. Double hidden layers showed better performance than a single hidden layer, while ...

Gb/s Bootstrap Transceiver in 40 nm CMOS for Referenceless and Lane-Independent Operation

An on-chip stochastic sigma-tracking eye-opening monitor (SSEOM) for background adaptive equalization is presented. The proposed SSEOM detects the BER-related eye opening area accurately with a feasible degree of time/area efficiency without an external microcontroller. In addition, the SSEOM determines the BER-optimal equalization parameters for both CTLE and DFE by incorporating a pattern-dependent eye-tracking scheme. Auxiliary data samplers are employed in parallel with data samplers to track link variations and adjust the equalization parameters in the background. A 28-Gb/s CDR including a SSEOM-based adaptive equalizer is fabricated in 40nm CMOS for an evaluation.