Kwangseok Han

Analytical drain thermal noise current model valid for deep submicron MOSFETs

In this paper, a physics-based MOSFET drain thermal noise current model valid for deep submicron channel lengths was derived and verified with experiments. It is found that the well-known /spl mu/Q/sub inv//L/sup 2/ formula, previously derived for long channels, remains valid for short channels. Carrier heating in the gradual channel region was taken into account implicitly with the form of diffusion noise source and then impedance field method taking velocity saturation effect was used to calculate the external drain thermal noise current. The derived model was verified by experimental noise for devices with channel lengths down to 0.18 /spl mu/m. Excellent agreement between measured and modeled drain thermal noise was obtained for the entire V/sub GS/ and V/sub DS/ bias regions.

The impact of semiconductor technology scaling on CMOS RF and digital circuits for wireless application

The impact of CMOS technology scaling on the various radio frequency (RF) circuit components such as active, passive and digital circuits is presented. Firstly, the impact of technology scaling on the noise and linearity of the low-noise amplifier (LNA) is thoroughly analyzed. Then two new circuits, i.e., CMOS complementary parallel push-pull (CCPP) circuit and vertical-NPN (V-NPN) circuit for direct-conversion receiver (DCR), are introduced. In CCPP, the high RF performance of pMOS comparable to nMOS provides single ended differential RF signal processing capability without the use of a bulky balun. The use of parasitic V-NPN bipolar transistor, available in triple well CMOS technology, has shown to provide more than an order of magnitude improvement in 1/f noise and dc offset related problems, which have been the bottleneck for CMOS single chip integration. Then CMOS technology scaling for various passive device performances such as the inductor, varactor, MIM capacitor, and switched capacitor, is discussed. Both the forward scaling of the active devices and the inverse scaling of interconnection layer, i.e., more interconnection layers with effectively thicker total dielectric and metal layers, provide very favorable scenario for all passive devices. Finally, the impact of CMOS scaling on the various digital circuits is introduced, taking the digital modem blocks, the various digital calibration circuits, the switching RF power amplifier, and eventually the software defined radio, as examples.

Complete high-frequency thermal noise modeling of short-channel MOSFETs and design of 5.2-GHz low noise amplifier

Taking a velocity saturation effect and a carrier heating effect in the gradual channel region, complete thermal noise modeling of short-channel MOSFETs including the induced gate noise and its correlation coefficients is presented and verified extensively with experimentally measured data. All of the four noise models have excellently predicted experimental data with maximal error less than 10% for the deep-submicron MOSFETs. Using these models and a simultaneous matching technique for both optimal noise and power, a low noise CMOS amplifier optimized for 5.2-GHz operation has been designed and fabricated. Experiments using an external tuner show that both NF/sub 50/ and NF/sub min/ are very close to 1.1 dB, which is an excellent figure of merit among reported LNAs.

Room temperature single electron effects in a Si nano-crystal memory

An MOS memory based on Si nano-crystals has been fabricated. We have developed a repeatable process of forming uniform, small-size and high-density Si nano-crystals and spherical nano-crystals of about 4.5 nm in diameter with density of 5/spl times/10/sup 11//cm/sup 2/ were obtained. Threshold voltage shift of 0.48 V corresponding to single electron storage in individual nano-crystals is obtained. For the first time, room temperature single electron effects are observed. These prove the feasibility of practical Si nano-crystal memory.

Characteristics of p-channel Si nano-crystal memory

In this work, the feasibility of p-channel nano-crystal memory with thin oxide in direct tunneling regime is demonstrated. By comparing the programming characteristics of devices with nano-crystals and devices without nano-crystals, the role of dots as storage node is presented. The programming and erasing mechanisms of p-channel nano-crystal memory were investigated by charge separation technique. For small gate programming voltage, hole tunneling component from inversion layer is dominant. However, valence band electron tunneling component from the valence band in the nano-crystal becomes dominant for large gate voltage. In case of erasing, the electron tunneling occurs from either the conduction band or the valence band. Finally, the comparison of retention between programmed holes and electrons shows that holes have longer retention time.

Si Nanocrystal Memory Cell with Room-Temperature Single Electron Effects

A metal oxide semiconductor (MOS) memory based on Si nanocrystals has been fabricated. We have developed a repeatable process for forming uniform, small and high-density Si nanocrystals by low pressure chemical vapor deposition (LPCVD). Spherical nanocrystals with a 4.5 nm average diameter and a density of 5×1011/cm2 were obtained. A single transistor memory-cell structure, with a change in threshold voltage of about 0.48 V, corresponding to single electron storage in individual nanocrystals and having the capability of long-term charge storage is fabricated and characterized. For the first time, the single electron effect at room temperature, which shows a saturation of threshold voltage in a range of gate voltages with a periodicity of ΔVGS≈1.7 V, corresponding to single and multiple electron storage is reported. These finding prove the feasibility of a practical nanocrystal memory with potential for significantly high density, low power, and fast reading properties.

Programming characteristics of p-channel Si nano-crystal memory

In this work, the programming characteristics of a p-channel nano-crystal memory is studied. The hole tunneling component from the inversion layer and the electron tunneling component from the valence band in the nano-crystal were separated successfully by independent measurement of the current at the body terminal and at the source/drain terminal of the memory. For small gate voltage, the hole tunneling current is dominant during programming. However, for large programming voltage, the valence band electron tunneling from the dot into the substrate becomes dominant. Finally, the comparison of retention characteristics between programmed holes and electrons shows that holes have longer retention time.

Characteristics of P-channel Si nano-crystal memory

The nano-crystal memory operates at low voltage compared to conventional flash memory due to thinner tunneling dielectrics, since the spacing between the Si dots suppresses the charge loss through lateral paths. Recently, N-channel nano-crystal memory has been reported to have good characteristics compared to EEPROM. In this paper, the characteristics of the P-channel nano-crystal memory, which stores holes as information, is presented for the first time.

A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS

This paper describes a low-power 100 Gigabit Ethernet transceiver IC compliant with IEEE802.3ba 100GBASE-LR4 in 40 nm CMOS. The proposed bidirectional full-duplex transceiver IC contains a total of eight 28 Gb/s CDRs. Each CDR lane incorporates phase-rotator-based delay- and phase-locked loop (D/PLL) architecture for enhanced jitter filtering. All the CDR lanes operate independently while sharing a single voltage-controlled oscillator and supporting referenceless clock acquisition. To reduce power consumption, a multidrop clock distribution scheme with single on-chip transmission-line (T-line) and quadrate RX and TX schemes without CML logic gates are incorporated. Embedded built-in self-test modules featuring a random accumulation jitter generator enables bit error rate (BER) and jitter tolerance self tests without any external equipment. The TX featuring a three-tap pre-emphasis provides a variable output swing ranging from 478 mVppd to 1.06 Vppd. RX equalizers employing a continuous-time linear equalizer and a one-tap decision feedback equalizer compensate for the channel loss up to 25 dB at the Nyquist rate. The measured RX input sensitivity for a BER of 10 -12 is 42 mVppd. The proposed IC consumes only 0.87 W at 28.0 Gb/s with a BER less than 10 -15 on PRBS31 testing. The power efficiency of the proposed transceiver is 3.9 mW/Gb/s, which is the best among the efficiencies achieved by recently published 25 Gb/s transceivers.

A Fully Integrated Low-Power High-Coexistence 2.4-GHz ZigBee Transceiver for Biomedical and Healthcare Applications

A fully integrated low-power high-coexistence 2.4-GHz ZigBee transceiver implemented in 90-nm CMOS technology is demonstrated. The two-point direct-modulation with a fractional- N synthesizer is adopted in the transmitter architecture. The transmitter can provide high output power of +9 dBm and excellent error vector magnitude of 5.1%. The direct conversion is used in receiver for simplicity and -97-dBm minimum receiver sensitivity is achieved. Current consumptions for a TX at +9-dBm output power and for an RX are 28.4 and 15.4 mA, respectively. Excellent coexistence is presented through wireless local area network interferer rejection performance.