Hyosup Won

A 0.87 W Transceiver IC for 100 Gigabit Ethernet in 40 nm CMOS

This paper describes a low-power 100 Gigabit Ethernet transceiver IC compliant with IEEE802.3ba 100GBASE-LR4 in 40 nm CMOS. The proposed bidirectional full-duplex transceiver IC contains a total of eight 28 Gb/s CDRs. Each CDR lane incorporates phase-rotator-based delay- and phase-locked loop (D/PLL) architecture for enhanced jitter filtering. All the CDR lanes operate independently while sharing a single voltage-controlled oscillator and supporting referenceless clock acquisition. To reduce power consumption, a multidrop clock distribution scheme with single on-chip transmission-line (T-line) and quadrate RX and TX schemes without CML logic gates are incorporated. Embedded built-in self-test modules featuring a random accumulation jitter generator enables bit error rate (BER) and jitter tolerance self tests without any external equipment. The TX featuring a three-tap pre-emphasis provides a variable output swing ranging from 478 mVppd to 1.06 Vppd. RX equalizers employing a continuous-time linear equalizer and a one-tap decision feedback equalizer compensate for the channel loss up to 25 dB at the Nyquist rate. The measured RX input sensitivity for a BER of 10 -12 is 42 mVppd. The proposed IC consumes only 0.87 W at 28.0 Gb/s with a BER less than 10 -15 on PRBS31 testing. The power efficiency of the proposed transceiver is 3.9 mW/Gb/s, which is the best among the efficiencies achieved by recently published 25 Gb/s transceivers.

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A four-parallel 10-Gb/s referenceless-and-masterless phase rotator-based transceiver is presented. Entire lanes operate independently just like the conventional voltage-controlled-oscillator-based parallel referenceless designs while saving power and area. The measured recovered-clock jitter in each lane is 1.24 psrms and the transceiver surpasses the OC-192 jitter-tolerance specification. The power efficiency of the proposed parallel transceiver fabricated in a 90-nm CMOS process is 6.325 mW/(Gb/s).

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This paper describes a 28-Gb/s receiver IC with self-contained adaptive equalization and sampling point control using an on-chip stochastic sigma-tracking eye-opening monitor (SSEOM). The proposed SSEOM accurately detects the bit-error-rate (BER)-related eye contour efficiently without the use of an external microcontroller. The SSEOM determines the BER-optimal sampling point and equalizer coefficients on the basis of pattern-filtered eye diagrams. It also features a background adaptation scheme for robust long-term operation by tracking temperature variations and device aging. The proposed SSEOM is integrated in a 28-Gb/s receiver that is designed to compensate for channel loss up to 25 dB at the Nyquist rate by using a continuous time linear equalizer (CTLE) and a one-tap decision feedback equalizer (DFE) together with an one-tap pre-emphasis at a transmitter. The time required for complete adaptation and the total power consumption are 364 ms and 43.9 mW, respectively. The proposed 28-Gb/s receiver is fabricated in 40 nm CMOS.

-Gb/s Referenceless-and-Masterless Phase Rotator-Based Parallel Transceiver in 90-nm CMOS

An automatic loop gain control algorithm (ALGC) for a bang-bang (BB) clock and data recovery (CDR) is proposed. The proposed algorithm finds the optimum loop gain using the autocorrelation of a BBPD output signal for minimum MSE performance. Mathematical proof of the algorithm is presented for both rotator-based and VCO-based CDRs with finite loop delay. A 25 Gb/s transceiver IC is fabricated using a 40 nm CMOS process to validate the performance of the algorithm. The power consumptions of TX and RX are 37.8 mW and 46.8 mW, respectively and the synthesized area implementing a digital loop filter together with the proposed ALGC occupies 140 μm × 170 μm.

A 28-Gb/s Receiver With Self-contained Adaptive Equalization and Sampling Point Control Using Stochastic Sigma-Tracking Eye-Opening Monitor

This paper presents the industrys first low-power 100-Gigabit Ethernet (GbE) multi-link gearbox (MLG) IC, which facilitates transport of independent 10-GbE and 40-GbE signals to 4×25G physical layers implementing 100GBASE-R. The IC consumes only 1.37-W while implementing complicated reverse gearbox functionality. The measured TX jitter from the 25-Gb/s lane is 1.6-psrms, and the recovered clock jitter is 0.5-psrms. The measured RX input sensitivity for a BER 10-12 is 42-mVppd. The proposed gearbox IC, fabricated in a 40nm CMOS process, occupies 3.7×3.4-mm2. The power consumption of RX and TX in 25G interfaces are 47-mW and 51-mW, respectively, and those of a 10G interfaces are 24-mW and 25-mW, respectively. Gearbox functionalities are verified with embedded self-test logics.

An Automatic Loop Gain Control Algorithm for Bang-Bang CDRs

In this paper, an RLGC model of a silicone rubber socket is proposed and compared with simulation results. Due to the reusability of the silicone rubber socket, it is suitable for a reliable test. In addition, its electrical performance is compared with that of conventional solder balls. The performance of the two are compared using measurements in both frequency and time domains. Their eye diagrams are nearly identical at the data rate of 28Gbps, which is the data rate of a single channel in a 100Gbps transceiver IC that consists of 4 parallel channels.

A 100-GbE reverse gearbox IC in 40nm CMOS for supporting legacy 10- and 40-GbE standards

An on-chip stochastic sigma-tracking eye-opening monitor (SSEOM) for background adaptive equalization is presented. The proposed SSEOM detects the BER-related eye opening area accurately with a feasible degree of time/area efficiency without an external microcontroller. In addition, the SSEOM determines the BER-optimal equalization parameters for both CTLE and DFE by incorporating a pattern-dependent eye-tracking scheme. Auxiliary data samplers are employed in parallel with data samplers to track link variations and adjust the equalization parameters in the background. A 28-Gb/s CDR including a SSEOM-based adaptive equalizer is fabricated in 40nm CMOS for an evaluation.

Modeling and measurement of high-bandwidth and high-density silicone rubber socket for 100Gbps transceiver IC test

This paper presents the design of an electronic dispersion compensator (EDC) for 10-Gb/s directly modulated distributed-feedback (DM-DFB) lasers. The proposed EDC overcomes the chirp-induced dispersion and achieves 2x reach extension in SMF-28 optical fiber.